Implementation of Sobel and Canny filters on FPGA

Implementation of Sobel and Canny filters on FPGA By Konstantin Martynov and Angel Carvajal 1

Motivation For Using FPGA Mostly robots orient around by finding edges created by objects to find or to avoid those objects. Edge detection done by convolution – very expensive operation in software. FPGA could be installed on a robot to make fast, low power, low latency edge detection with maximum speed. 2

Order Of Operations Convert To Grayscale Apply Sobel Filter Apply Canny Filter 3

Test Plan The same function with the same approximations discussed further implemented in matlab and FPGA output should give exactly the same answer. However, To compare effect of approximations correlation coefficient may be used : 4

Sobel Filter : Gradient Field Goal: Enhance Edges by creating gradient field. 5

Sobel Filter : Extracting Magnitude and Direction Goal: Calculate Values needed by Canny Filter 6

Sobel Filter : Approximation For Direction 7

Canny Filter: Narrowing Lines Goal: Make width of Edge equal to 1 pixel 8

High Level Design FPGA Grayscale Image From Host (. bin) Filtered Image To Host (. txt) Input Image Sce. Mi DRAM Filtered Image 64 Main Program Cycle Count Sobel Filter 512 10*W Canny Filter 8*W 9

Microarchitecture: Sobel Filter in. Vector r 1 Wx 8 3*(W+2)*8 in. FIFO N_loads, Reg_filled ? r 1<- r 2; r 2<- r 3; Interface : Sobel Filter Hx. W out. Vector Magnitude r 2 r 3 3*(W+2)*8 W*8 *Gx Angle *Gy W*2 out. FIFO in. Vector - Vector#(w, Bit#(8)) out. Vector -Vector#(w, Bit#(10)) r 1 -r 3 – Reg#(W+2) N_loads – Int#(16) Reg_filled – Bool#() 10

Microarchitecture: Canny Filter Interface: Canny Filter Height (H) Width (W) Threshold (T) R 1, R 2, R 3 – Size(W+2) Cannyin = Vector#(w, Int#(10)) Cannyout = Vector#(w, Int#(8)) N_loads – Int#(16) Reg_filled – Bool#() Wx 8 Cannyin R 1 3*(W+2)x 8 R 2 R 3 Wx 2 N_loads, Reg_filled Non-Max Suppression Wx 8 Cannyout Wx 8 out. FIFO input. FIFO Reg_filled ? R 1<- R 2; R 2<- R 3; 11

Results : Easy implementation 12

Improved Microarchitecture Changes : • Use 64 byte inputs instead of W byte inputs. Reduces amount of Hardware dramatically • Use FIFO inside of interface. This separates registers change from computations in. Vector r 1 512 r 2 1584 Row_count, col_count r 1<- r 2; r 2<- r 3; Interface : Sobel Filter Hx. W r 2 s. FIFO out. Vector Magnitude Angle r 3 in. FIFO 512 *Gx *Gy 128 out. FIFO in. Vector - Vector#(64, Bit#(8)) out. Vector -Vector#(64, Bit#(10)) r 1 -r 3 – Reg#(W+2) Row_count – bit#(16) Col_count – Bit#(16) 13

Improved Microarchitecture : Registers 64 pix 1 pix - Available Data - Data being converted 14

Results : Improved implementation 15

Future Work 1. Implement Canny filter that uses both lower and higher threshold to keep track of continuous edges. 2. If non compressed data used, output could be as stream of coordinates with nonzero pixel. This is efficient, because after canny filter there is very small fraction of white pixels. 3. Image compression on FPGA to take input and output image formats. 4. Video compression on FPGA to convert video formats. 5. Implement corner detection 16