Implementation of FloatingPoint Vector Signal Image Processing Library

Implementation of Floating-Point Vector Signal Image Processing Library Functions on FPGA-Based Reconfigurable Computers Using High-Level Languages Robin Bruce, Stephen Marshall, and Malachy Devlin 1

Overview of VSIPL • Vector Signal Image Processing Library • Developed to give high-performance embedded system developers an industry-standard API • Application Developers • Provided with abstraction from hardware specifics • Applications easily ported to new hardware • Hardware Developers Application • Create VSIPL implementations Hardware VSIPL 2

Why VSIPL for FPGAs? l l FPGAs vs. Commodity microprocessors Gate density of FPGAs has increased • Floating-point now viable (25 – 50 GFLOPS) • Peak FLOPS are the constraint to performance, not memory bandwidth l Consideration of embedded environment l Superior I/O capabilities • Lower power consumption of FPGAs • Smaller size and weight when deployed in the field 3

Why Use High-Level Languages? l l l VSIPL functions are best implemented as maximally-pipelined architectures Resource sharing between nonconcurrentlyexecuting functions is desirable Scale of library makes it impractically large for an implementation using VHDL l High-Level Languages are therefore the natural choice to implement VSIPL using FPGAs 4

Implementation Model PCI / PCI -X Host l l Control Memory Management Scalar Operations Majority of lines in VSIPL program executed here FPGA Fabric l l l Input/Output Vector & Matrix Operations Majority of computation performed here 5

Example Implementation l l l Implemented on an FPGA a unit that could carry out the operations involved in pulse compression C-program on host controls tri-mode unit on FPGA Significant speedup over microprocessor Real. A/ Result Imag. A/ Result size log 2 size mode scale Real. B Imag. B Roots_u 1 Tri-mode Functional Unit Mode 1 = FFT Mode 2 = IFFT Mode 3 = Complex Multiply Pulse Compression Unit 6 Roots_u 2