IEEE P 1687 Obstacle Course John Potter Sr

In this session, you will see. . . • What is IEEE P 1687? • ICL and PDL • Example Network • Reset Architecture of an Instrument Network • Case Sensitivity, case SENSITIVITY, CASe … • Tracing : BSDL vs. P 1687 • Instrument Concurrency • Parameter Resolution • i. Apply Ambiguity © 2010, ASSET Inter. Tech, Inc. 2

What is IEEE P 1687? • A proposed IEEE standard for the access of embedded instruments • Embedded Instruments can be for test, debug, functional configuration, yield monitors, etc… • Three important parts of the standard • Hardware Architecture Description (ICL) • Vector/Procedure Language (PDL) © 2010, ASSET Inter. Tech, Inc. 3

ICL and PDL? • ICL • Instrument Connectivity Language • Describe a 1687 Network (may include dynamic chains) • Describe Instrument connection to the network • Link Instrument vectors (PDL) • PDL • Procedure Description Language • Describe behavioral functionality • Create standard set of instrument interface operations © 2010, ASSET Inter. Tech, Inc. 4

TAP SM TAP IR TCK MBIST_1 TDI TDO BSDL Description bit[0] L 0_GWR bit[1] Gateway Hierarchy Lev-0 © 2010, ASSET Inter. Tech, Inc. i. MBIST_1 Gateway_1 LBIST_0 GWEN i. MBIST_0 Daisy-Chained Instrument Interfaces JTAG Regs TMS Static Signals MBIST_0 TAP IR With GWEN Instruction Register Bits P 1687 Serial Instrument Network Interface Hierarchy Level-1 5 i. LBIST_0 Instrument

Reset Architecture of an Instrument Network • Soft Reset – Scan in Reset. Value of Update Cells • Hard Reset – Global • TLR • Efficient and to the point • Entire network affected • Invoked by controlling process • Hard Reset – Local • Network Instruction Bit (NIB) • Special, self-clearing network bit? • Localized / Isolated / Targeted network reset • i. Reset…Aye, Aye…AARRRGH Matey © 2010, ASSET Inter. Tech, Inc. 6

Case Sensitivity of ICL and PDL • BSDL is Case In-sensitive • Verilog (chip design language) can be case sensitive • Potential exists to generate ICL from Verilog • Potential exists to generate Verilog from ICL • ICL Access. Link describes relationship to BSDL • BSDL Entity Name • Instruction Name • Attachment to simulation • If ICL is case sensitive, so goes PDL… • Case sensitivity is more about the content than the keywords © 2010, ASSET Inter. Tech, Inc. 7

Tracing: BSDL vs. ICL • BSDL • One JTAG Instruction = One Test Data Register (TDR) • All Data Register bits are in the scan path • Scan Path has a fixed Scan. Length • ICL • One JTAG Instruction = One or more TDRs • Recommend PRIVATE Instruction • Scan Path has dynamically changing Scan. Length • Scan Path depends on inferred connections • Scan Path must be calculated after EACH Update. DR • Quiz: Where do bear tracks take you? © 2010, ASSET Inter. Tech, Inc. 8

Bear Tracks Lead to… © 2010, ASSET Inter. Tech, Inc. 9

Instrument Concurrency • Run at the same time • Start at the same time • PDL Lock-Step • So, the instrument finished… • Keep it in the network? • Take it out of the network? © 2010, ASSET Inter. Tech, Inc. 10

Parameters, Parameters… © 2010, ASSET Inter. Tech, Inc. 11

Parameter Resolution • Readability versus Reusability • Readable: Explicit Port and Register sizing • Generic: Parameterized Port and Register sizing • Multi-Level Parameter Passing leads to obfuscated intent • So goes parameters, so goes flattening the network to resolve parameter references • It looked good on paper… © 2010, ASSET Inter. Tech, Inc. 12

i. Apply Ambiguity • Writes are sticky – Reads are NOT sticky • Random versus Literal Scan. DR content • Instruction Co-Dependence • Discovering PDL intent matches ICL content © 2010, ASSET Inter. Tech, Inc. 13

i. Apply Perspective – The Stage Reg. A[3: 0] = Sig_A, Sig_B, Sig_C, Sig_D

i. Apply Perspective – Act 1: The User (Register) SDR 8 TDI (35) …;

i. Apply Perspective – Act 1: The User (Signal) SDR 8 TDI (35) …; i. Write Sig_A 0 b 0; i. Write Sig_B 0 b 0; i. Write Sig_C 0 b 3; i. Write Sig_D 0 b 3; i. Write Sig_E 0 b 0; i. Write Sig_F 0 b 1; i. Write Sig_G 0 b 0; i. Write Sig_H 0 b 1; i. Apply; © 2010, ASSET Inter. Tech, Inc. 16

i. Apply Perspective – Act 2: WG Member X SDR 8 TDI (30) …;

i. Apply Perspective – Act 3: Software Engineer SDR 8 TDI (00) …; SDR 8 TDI (20) …; SDR 8 TDI (33) …; SDR 8 TDI (30) …; SDR 8 TDI (34) …; SDR 8 TDI (30) …; SDR 8 TDI (35) …; i. Write Sig_A 0 b 0; i. Write Sig_B 0 b 0; i. Write Sig_C 0 b 3; i. Write Sig_D 0 b 3; i. Write Sig_E 0 b 0; i. Write Sig_F 0 b 1; i. Write Sig_G 0 b 0; i. Write Sig_H 0 b 1; i. Apply; © 2010, ASSET Inter. Tech, Inc. 18

Good things come… • PDL is WAY, WAY easier to write than SVF!!! • Allowance of Tcl finally gives true programmability via JTAG • Portable and Reusable Instrument “patterns” • Scheduling © 2010, ASSET Inter. Tech, Inc. 19