ICDFN Hangzhou 81606 Design for Manufacturability with Deep

ICDFN, Hangzhou, 8/16/06 Design for Manufacturability with Deep Subwavelength Lithography David Z. Pan Dept. of Electrical and Computer Engineering University of Texas at Austin http: //www. cerc. utexas. edu/utda 1

CMOS & Nanotechnology t Nanoscale CMOS is nano-technology (and a real one) Ø Heavy research on “nano” alternatives, but will it replace CMOS, ever? [Prof. Hu’s talk yesterday, “Post-CMOS? ”] Ø [ITRS’ 05]: scaling as usual for another 10 -15 years Ø [Borkar, DAC’ 06]: nothing to replace CMOS in the next 15 years Ø Hybrid CMOS/beyond-CMOS t Historical projection [Prof. T. P. Ma, Yale Univ. , EITC’ 06] Ø Ø Ø Stone age: 5000 years Bronze age: 2500 years Iron age: 1500 years Silicon age [1947 -]: 1000 years! My 2 cents: End of CMOS scaling != End of silicon age or semiconductor industry (innovations from all aspects) 2

Yield Loss Projection Scary [Courtesy IBS] 3

Lithography Basics Illumination Wavelength λ Optical Mask Optical system Immersion Wafer (photoresist, etching…) 4

WYS != WYG 227 nm @ 0. 85 NA 136 nm 114 nm 91 nm 68 nm The RET solutions…. 68 nm “Full” OPC Add scatter bars Add biasing 5 better OAI 6% Att-PSM OAI (Source: ASML)

Challenges are REAL t 193 nm lithography will continue as the main chip manufacturing workhorse for at least 5 -7 years (thanks to RET and immersion litho…) Ø 45 nm and even 32 nm nodes Ø IBM news (02/06) of 29. 9 nm pattern Ø Nanolithography still many challenges • EUVL, E-Beam, nano-imprint… t Live in deep sub-wavelength era Ø On top of DSM challenges Ø Has to be considered altogether t Other DFM effects: CMP, VIA failure, … 6

Call for True DFM t Current “DFM” still mostly post-D(esign): data prep Ø Often too late to fix all the problems Ø Little flexibility Ø Not much design-intent contained Ø No global picture and tradeoff with other objectives èTrue DFM: model/predict downstream MFG/Litho effects into analysis and optimization è The root cause of litho-induced layout-dependent variations è Improve yield (both functional and parametric), with less cost, faster time to market… 7

Overall Objective/Highlights We aim at holistic modeling, characterization, and optimization of systematic and layout-dependent variations t Bottom-up framework to tackle the heart of DFM t Ø Variational lithography modeling to predict layoutdependent CD variations [DAC’ 05, DAC’ 06] Ø Non-rectangular gate characterizations [ICCAD’ 06] Ø Statistical/static timing/power analysis [ICCAD’ 06] Ø Lithography/CMP aware physical design [DAC’ 05], [DAC’ 06], [ICCAD’ 06] Ø Variation-tolerant design [ICCAD’ 05], [ISPD 05/06]… 8

Overall Objective/Highlights We aim at holistic modeling, characterization, and optimization of systematic and layout-dependent variations t Bottom-up framework to tackle the heart of DFM t Ø Variational lithography modeling to predict layoutdependent CD variations [DAC’ 05, DAC’ 06] Ø Non-rectangular gate characterizations [ICCAD’ 06] Ø Statistical/static timing/power analysis [ICCAD’ 06] Ø Lithography/CMP aware physical design [DAC’ 05], [DAC’ 06], [ICCAD’ 06] Ø Variation-tolerant design [ICCAD’ 05], [ISPD 05/06]… 9

Lithography Modeling t Fast yet high-fidelity lithography modeling essential Ø Our approach: design-oriented (vs. process-oriented) [Mitra et al, DAC’ 05] t Process variations will affect printed image Ø Dosage, focus, mask, … t Variational lithography modeling [Yu et al. , DAC’ 06] Ø Our approach: variational kernel decomposition with moment expansion (vs. process window sampling) 10

Model Validation t Validated with PROLITH (orders of 106 faster) Our simulator PROLITH 11

RADAR: RET-Aware Detailed Routing [Mitra et al, DAC’ 05] t Raise lithography modeling up to design implementation level Ø Model-based vs. rule-based Conventional approaches to “separate” design from manufacturing – RULES t Rules are starting running out of steam from 65 nm t Ø Exploding number of rules Ø VERY complicated rules (have you seen a Law book? ) Ø Not accurate any more… t Use our design-oriented lithography simulation to generate litho-hotspots and guide routing 12

Lithography-aware Routing on a 65 nm Industry Design Initial routing (after design closure) 40% litho hotspot reduction 13

Non-Rectangular Gates t Gate shapes are not rectangular any more Ø Printability limitation due to litho (WYS != WYG) Ø Process Variations: dose, defocus, etching… Ø Non-rectangular channel… t Geometry => electrical characterization Ø Timing/leakage may be affected significantly [Yang et al, DAC’ 05] 14

Previous Works t t Gate slicing Equivalent gate length (EGL) L W (a) (b) t Two EGLs, for ON (timing) and OFF (leakage) t However, EGL-based model has fundamental limitation for coherent timing/power analysis Hard to pick the right EGL a priori during circuit simulation Certain level of non-rectangularity already considered during model parameter extraction (e. g. , BSIM) but not considered by EGL t t 15

Our Unified Current-Based Model [Shi et al, ICCAD’ 06] t Each device is attached with an artificial modeling card Ø Input: post-litho gate contour and Vd, Vg, Vs Ø Output: Id, Is modification Ø Slicing & pre-characterization of I-V curves Ø Generic current model (hybrid table + analytical) Ø Impact of process variation can be simulated accurately t t Unified model for timing/leakage Can incorporate other effects (e. g. , parameter extraction of non-rectangular gates) 16

Simulation Results Inverter Delay Comparison Rising Delay Falling Delay (ps) Diff. Our Model 57. 7 - 59. 0 - ON EGL 58. 8 1. 87% 57. 8 -2. 09% Static Power Dissipation Static 1 Static 2 (n. W) dif. Our Model 24. 3 - 29. 2 - ON EGL 26. 5 9. 05% 31. 1 6. 67% OFF EGL 62. 2 156% 36. 6 25. 3% 17

Other DFM Issues t Lithography interact with CMP Ø CMP => defocus t CMP-Aware Routing [ICCAD’ 06] Ø Density-driven with predictive CMP model Ø Enhance the state-of-the-art Box. Router [DAC’ 06 BPA candidate] Ø 7. 5 -10% reduction in thickness var. Ø 7 -10% improvement in timing t DFM in context of DSM (timing, power/leakage, reliability…) 18

Conclusion Holistic nanometer design + manufacturing closure t Much more closer collaborations to break the redbrick wall t Ø Between different “camps”: designer, CAD, process Ø Between academia and industry Ø CMOS and beyond CMOS Process Technology Design Technology 19

Silicon Age - 1000 years to go 20

Acknowledgment Support from SRC, IBM, Fujitsu, Sun, Intel, KLATencor and Sigma-C t Graduate students at UTDA: Minsik Cho, Joydeep Mitra, Anand Ramalingam, Sean Shi, Gang Xu, Peng Yu t Collaboration/discussion with Dr. Chris Mack and Dr. Warren Grobman t 21