IAS 0600 Digital Systems Design with VHDL Digitaalssteemide

IAS 0600 Digital Systems Design with VHDL Digitaalsüsteemide disain VHDL-s Course Overview Alexander Sudnitson Tallinn University of Technology

Administrative Aleksander Sudnitsõn (Alexander Sudnitson) Department of Computer Systems (Arvutisüsteemide instituut) Associate Professor (dotsent) ICT-503 aleksander. sudnitson@taltech. ee Tel. +372 5092356 www. pld. ttu. ee/~alsu 2

Administrative Assistant: Dimitri Mihhailov, research scientist, Ph. D Department of Computer Systems (Arvutisüsteemide instituut) ICT-505 dmitri. mihhailov@taltech. ee 3

Preliminary knowledge in Digital (System) Design in Bachelor' degree of study. 4

Course goals ü to elaborate knowledge of the design process from design description in VHDL through functional simulation, synthesis, timing simulation, and PLD (FPGA) programming; ü to gain experience in designing and verifying digital systems using synthesis and simulation tools; ü to provide students theory and practice of rapid prototyping of digital systems in a laboratory environment; 5

Outcomes üto proceed from a digital system description in VHDL to its implementation in a PLD (FPGA) using of a number of computer-aided design software tools; üto understand how to interpret design tool outputs in evaluating alternative system designs for a specific set of requirements, and how to use the knowledge gained to improve the design. 6

Why is this course worth taking? ü VHDL for synthesis: one of the most sought-after skills ü knowledge of state-of-the-art tools used in the industry ü knowledge of the modern FPGA & ASIC technologies ü unique knowledge and practical skills that make you competitive on the job market

Main topics ü ü The course is based on the development of a real-world projects and case studies Synthesizable VHDL Digital systems design methodology using VHDL and PLD (FPGA) FPGAs as means for building reconfigurable systems Rapid prototyping of digital systems. 8

Course resources www. pld. ttu. ee/~alsu IAS 0600 Digital Systems Design with VHDL (LECTURES) Digitaalsüsteemide disain VHDL-s IAS 0600 l Digital Systems Design with VHDL (WORKSHOPS) Digitaalsüsteemide disain (LABS) 9

Lectures Lecture: Thuesday 16. 00 - 17. 30 http: //ati. ttu. ee/~alsu/IAS 0600. html 10

Slides http: //ati. ttu. ee/~alsu/IAS 0600. html Lecture slides (to be published before each lecture). Auxiliary material: Digital Systems Modelling and Synthesis http: //www. ati. ttu. ee/IAY 0340/ 11

Labs A. Thuesday B. Wednesday 17. 45 - 19. 15 19. 30 - 21. 00 http: //ati. ttu. ee/~alsu/IAS 0600 l. html IAS 0600 l 12

Labs Xilinx FPGA Tools The laboratory assignments are done using the Xilinx ISE Software and Vivado. simulation synthesis implementation Digilent Nexys 4 FPGA Board 13

Passing a Lab Every completed experiment (project) must be presented to Assistant (D. Mihhailov), who will evaluate student’s results and effort Each lab is passed in three steps: Step 1: Visual demonstration Step 2: Submission of the report Step 3: Defence/discussion of the report Labs should be done individually. 14

Grading To stimulate the student’s activity a project-based evaluation approach is adopted. Grading consists of control of knowledge in examinations and of the demonstration of the projects and the quality of a written reports (up to 60 points in final grade for doing labs). Exam gives max 40 points (30+10). “LEARN BY DOING” Learning By Example Using VHDL (with FPGA Evaluation Boards) 15

Grading All Labs give 60 points to the final grade (each lab gives 10 points) No points are awarded if the lab is not passed within deadlines (as specified above and in Lab Syllabus) Additional 5 points (Bonus 1) are awarded if labs 2 -5 are passed until 20. 11. 2019 Additional 5 points (Bonus 2) are awarded if labs 2 -7 are passed until 20. 12. 2019 Intermediate exam is conducted on 14. 11. 2019 in ICT-A 1 at 16: 00 16

Labs schedule - Tutorials Week 1: Tutorial (part 1) 2: Tutorial (part 2) - Labs (first half) Week 3: Lab 2 Week 5: Lab 3 Week 7: Lab 4 Week 9: Lab 5 Week 10 14. 11. 2019, 16: 00 -17: 30 Intermediate exam Bonus 1 is awarded if labs 2 -5 are passed until 20. 11. 2019 - Labs (second half) Week 11: Lab 6 Week 13: Lab 7 Bonus 2 is awarded if labs 2 -5 are passed until 20. 12. 2019 17

Textbooks Raj, A. Arockia Bazil. FPGA-Based Embedded System Developer´s Guide, CRC Press, 2018. Short K. L. VHDL for Engineers, Pearson Education, Inc. , 2009, 2013. Chu P. P. FPGA Prototyping Using VHDL Examples: Xilinx Spartan-3 Version, Jonh, Willey & Sons, 2008. Pedroni V. A. Circuit Design and Simulation with VHDL, Massachusetts Institute of Technology, 2010. Sarah L. Harris & David M. Harris, "Digital Design and Computer Architecture“, Elsevier, 2016. Skljarov V. , Skliarova I. , Sudnitson A. Design of FPGAbased Circuits using Hierarchical Finite State Machines. TUT Press, Tallinn, 2012, 240 p. 18