IA32 Architecture COE 205 Computer Organization and Assembly
IA-32 Architecture COE 205 Computer Organization and Assembly Language Computer Engineering Department King Fahd University of Petroleum and Minerals
Presentation Outline v Basic Computer Organization v Intel Microprocessors v IA-32 Registers v Instruction Execution Cycle v IA-32 Memory Management IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 2
Basic Computer Organization v Since the 1940's, computers have 3 classic components: ² Processor, called also the CPU (Central Processing Unit) ² Memory and Storage Devices ² I/O Devices v Interconnected with one or more buses v Bus consists of data bus ² Data Bus registers ² Address Bus ² Control Bus Processor (CPU) ALU CU Memory I/O Device #1 I/O Device #2 clock control bus address bus IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 3
Processor v Processor consists of ² Datapath § ALU § Registers ² Control unit v ALU ² Performs arithmetic and logic instructions v Control unit (CU) ² Generates the control signals required to execute instructions v Implementation varies from one processor to another IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 4
Clock v Synchronizes Processor and Bus operations v Clock cycle = Clock period = 1 / Clock rate Cycle 1 Cycle 2 Cycle 3 v Clock rate = Clock frequency = Cycles per second ² 1 Hz = 1 cycle/sec 1 KHz = 103 cycles/sec ² 1 MHz = 106 cycles/sec 1 GHz = 109 cycles/sec ² 2 GHz clock has a cycle time = 1/(2× 109) = 0. 5 nanosecond (ns) v Clock cycles measure the execution of instructions IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 5
Memory v Ordered sequence of bytes ² The sequence number is called the memory address v Byte addressable memory ² Each byte has a unique address ² Supported by almost all processors v Physical address space ² Determined by the address bus width ² Pentium has a 32 -bit address bus § Physical address space = 4 GB = 232 bytes ² Itanium with a 64 -bit address bus can support § Up to 264 bytes of physical address space IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 6
Address Space is the set of memory locations (bytes) that can be addressed IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 7
Memory Unit v Two Control Signals v Address Bus ² Address is placed on the address bus ² Read ² Address of location to be read/written ² Write v Data Bus ² Data is placed on the data bus IA-32 Architecture ² Control whether memory should be read or written COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 8
Memory Read and Write Cycles v Read cycle 1. Processor places address on the address bus 2. Processor asserts the memory read control signal 3. Processor waits for memory to place the data on the data bus 4. Processor reads the data from the data bus 5. Processor drops the memory read signal v Write cycle 1. Processor places address on the address bus 2. Processor asserts the memory write control signal 3. Processor places the data on the data bus 4. Wait for memory to store the data (wait states for slow memory) 5. Processor drops the memory write signal IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 9
Reading from Memory v Multiple clock cycles are required v Memory responds much more slowly than the CPU ² Address is placed on address bus ² Read Line (RD) goes low, indicating that processor wants to read ² CPU waits (one or more cycles) for memory to respond ² Read Line (RD) goes high, indicating that data is on the data bus IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 10
Memory Devices v ROM = Read-Only Memory ² Stores information permanently (non-volatile) ² Used to store the information required to startup the computer ² Many types: ROM, EPROM, EEPROM, and FLASH ² FLASH memory can be erased electrically in blocks v RAM = Random Access Memory ² Volatile memory: data is lost when device is powered off ² Dynamic RAM (DRAM) § Inexpensive, used for main memory, must be refreshed constantly ² Static RAM (SRAM) § Expensive, used for cache memory, faster access, no refresh ² Video RAM (VRAM) § Dual ported: read port to refresh the display, write port for updates IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 11
Memory Hierarchy v Registers ² Fastest storage elements, stores most frequently used data ² General-purpose registers: accessible to the programmer ² Special-purpose registers: used internally by the microprocessor v Cache Memory ² Fast SRAM that stores recently used instructions and data lle rs ma sp ee d, s he r hig COE 205 – Computer Organization and Assembly Language – KFUPM yte rb disk storage pe main memory t os IA-32 Architecture cache memory c er v Disk Storage registers low v Main Memory (DRAM) ² Permanent magnetic storage for files ize ² Recent processors have 2 levels © Muhamed Mudawar – slide 12
Magnetic Disk Storage Disk Access Time = Seek Time + Rotation Latency + Transfer Time Read/write head Sector Actuator Recording area Seek Time: head movement to the desired track (milliseconds) Rotation Latency: disk rotation until desired sector arrives under the head Transfer Time: to transfer one sector IA-32 Architecture Track 2 Track 1 Track 0 Arm Direction of rotation Platter Spindle COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 13
Example on Disk Access Time v Given a magnetic disk with the following properties ² Rotation speed = 7200 RPM (rotations per minute) ² Average seek = 8 ms, Sector = 512 bytes, Track = 200 sectors v Calculate ² Time of one rotation (in milliseconds) ² Average time to access a block of 32 consecutive sectors v Answer ² Rotations per second = 7200/60 = 120 RPS ² Rotation time in milliseconds = 1000/120 = 8. 33 ms ² Average rotational latency = time of half rotation = 4. 17 ms ² Time to transfer 32 sectors = (32/200) * 8. 33 = 1. 33 ms ² Average access time = 8 + 4. 17 + 1. 33 = 13. 5 ms IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 14
I/O Controllers v I/O devices are interfaced via an I/O controller ² I/O controller uses the system bus to communicate with processor ² I/O controller takes care of low-level operation details IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 15
Next. . . v Basic Computer Organization v Intel Microprocessors v IA-32 Registers v Instruction Execution Cycle v IA-32 Memory Management IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 16
Intel Microprocessors v Intel introduced the 8086 microprocessor in 1979 v 8086, 8087, 8088, and 80186 processors ² 16 -bit processors with 16 -bit registers ² 16 -bit data bus and 20 -bit address bus § Physical address space = 220 bytes = 1 MB ² 8087 Floating-Point co-processor ² Uses segmentation and real-address mode to address memory § Each segment can address 216 bytes = 64 KB ² 8088 is a less expensive version of 8086 § Uses an 8 -bit data bus ² 80186 is a faster version of 8086 IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 17
Intel 80286 and 80386 Processors v 80286 was introduced in 1982 ² 24 -bit address bus 224 bytes = 16 MB address space ² Introduced protected mode § Segmentation in protected mode is different from the real mode v 80386 was introduced in 1985 ² First 32 -bit processor with 32 -bit general-purpose registers ² First processor to define the IA-32 architecture ² 32 -bit data bus and 32 -bit address bus ² 232 bytes 4 GB address space ² Introduced paging, virtual memory, and the flat memory model § Segmentation can be turned off IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 18
Intel 80486 and Pentium Processors v 80486 was introduced 1989 ² Improved version of Intel 80386 ² On-chip Floating-Point unit (DX versions) ² On-chip unified Instruction/Data Cache (8 KB) ² Uses Pipelining: can execute up to 1 instruction per clock cycle v Pentium (80586) was introduced in 1993 ² Wider 64 -bit data bus, but address bus is still 32 bits ² Two execution pipelines: U-pipe and V-pipe § Superscalar performance: can execute 2 instructions per clock cycle ² Separate 8 KB instruction and 8 KB data caches ² MMX instructions (later models) for multimedia applications IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 19
Intel P 6 Processor Family v P 6 Processor Family: Pentium Pro, Pentium II and III v Pentium Pro was introduced in 1995 ² Three-way superscalar: can execute 3 instructions per clock cycle ² 36 -bit address bus up to 64 GB of physical address space ² Introduced dynamic execution § Out-of-order and speculative execution ² Integrates a 256 KB second level L 2 cache on-chip v Pentium II was introduced in 1997 ² Added MMX instructions (already introduced on Pentium MMX) v Pentium III was introduced in 1999 ² Added SSE instructions and eight new 128 -bit XMM registers IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 20
Pentium 4 and Xeon Family v Pentium 4 is a seventh-generation x 86 architecture ² Introduced in 2000 ² New micro-architecture design called Intel Netburst ² Very deep instruction pipeline, scaling to very high frequencies ² Introduced the SSE 2 instruction set (extension to SSE) § Tuned for multimedia and operating on the 128 -bit XMM registers v In 2002, Intel introduced Hyper-Threading technology ² Allowed 2 programs to run simultaneously, sharing resources v Xeon is Intel's name for its server-class microprocessors ² Xeon chips generally have more cache ² Support larger multiprocessor configurations IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 21
Pentium-M and EM 64 T v Pentium M (Mobile) was introduced in 2003 ² Designed for low-power laptop computers ² Modified version of Pentium III, optimized for power efficiency ² Large second-level cache (2 MB on later models) ² Runs at lower clock than Pentium 4, but with better performance v Extended Memory 64 -bit Technology (EM 64 T) ² Introduced in 2004 ² 64 -bit superset of the IA-32 processor architecture ² 64 -bit general-purpose registers and integer support ² Number of general-purpose registers increased from 8 to 16 ² 64 -bit pointers and flat virtual address space ² Large physical address space: up to 240 = 1 Terabytes IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 22
CISC and RISC v CISC – Complex Instruction Set Computer ² Large and complex instruction set ² Variable width instructions ² Requires microcode interpreter § Each instruction is decoded into a sequence of micro-operations ² Example: Intel x 86 family v RISC – Reduced Instruction Set Computer ² Small and simple instruction set ² All instructions have the same width ² Simpler instruction formats and addressing modes ² Decoded and executed directly by hardware ² Examples: ARM, MIPS, Power. PC, SPARC, etc. IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 23
Next. . . v Basic Computer Organization v Intel Microprocessors v IA-32 Registers v Instruction Execution Cycle v IA-32 Memory Management IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 24
Basic Program Execution Registers v Registers are high speed memory inside the CPU ² Eight 32 -bit general-purpose registers ² Six 16 -bit segment registers ² Processor Status Flags (EFLAGS) and Instruction Pointer (EIP) 32 -bit General-Purpose Registers EAX EBP EBX ESP ECX ESI EDX EDI 16 -bit Segment Registers EFLAGS EIP IA-32 Architecture CS ES SS FS DS GS COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 25
General-Purpose Registers v Used primarily for arithmetic and data movement ² mov eax, 10 move constant 10 into register eax v Specialized uses of Registers ² EAX – Accumulator register § Automatically used by multiplication and division instructions ² ECX – Counter register § Automatically used by LOOP instructions ² ESP – Stack Pointer register § Used by PUSH and POP instructions, points to top of stack ² ESI and EDI – Source Index and Destination Index register § Used by string instructions ² EBP – Base Pointer register § Used to reference parameters and local variables on the stack IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 26
Accessing Parts of Registers v EAX, EBX, ECX, and EDX are 32 -bit Extended registers ² Programmers can access their 16 -bit and 8 -bit parts ² Lower 16 -bit of EAX is named AX ² AX is further divided into § AL = lower 8 bits § AH = upper 8 bits v ESI, EDI, EBP, ESP have only 16 -bit names for lower half IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 27
Special-Purpose & Segment Registers v EIP = Extended Instruction Pointer ² Contains address of next instruction to be executed v EFLAGS = Extended Flags Register ² Contains status and control flags ² Each flag is a single binary bit v Six 16 -bit Segment Registers ² Support segmented memory ² Six segments accessible at a time ² Segments contain distinct contents § Code § Data § Stack IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 28
EFLAGS Register v Status Flags ² Status of arithmetic and logical operations v Control and System flags ² Control the CPU operation v Programs can set and clear individual bits in the EFLAGS register IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 29
Status Flags v Carry Flag ² Set when unsigned arithmetic result is out of range v Overflow Flag ² Set when signed arithmetic result is out of range v Sign Flag ² Copy of sign bit, set when result is negative v Zero Flag ² Set when result is zero v Auxiliary Carry Flag ² Set when there is a carry from bit 3 to bit 4 v Parity Flag ² Set when parity is even ² Least-significant byte in result contains even number of 1 s IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 30
Floating-Point, MMX, XMM Registers v Floating-point unit performs high speed FP operations v Eight 80 -bit floating-point data registers ² ST(0), ST(1), . . . , ST(7) ² Arranged as a stack ² Used for floating-point arithmetic v Eight 64 -bit MMX registers ² Used with MMX instructions v Eight 128 -bit XMM registers ² Used with SSE instructions IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 31
Next. . . v Basic Computer Organization v Intel Microprocessors v IA-32 Registers v Instruction Execution Cycle v IA-32 Memory Management IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 32
Infinite Cycle Instruction Execute Cycle Instruction Fetch Obtain instruction from program storage Instruction Decode Determine required actions and instruction size Operand Fetch Locate and obtain operand data Execute Compute result value and status Writeback Result IA-32 Architecture Deposit results in storage for later use COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 33
Instruction Execution Cycle – cont'd PC v Instruction Fetch v Instruction Decode I 1 memory op 1 op 2 read program I 2 I 3 I 4 fetch registers v Operand Fetch . . . registers I 1 write v Result Writeback decode v Execute instruction register flags ALU execute (output) IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 34
Pipelined Execution v Instruction execution can be divided into stages v Pipelining makes it possible to start an instruction before completing the execution of previous one Stages Cycles 1 2 3 4 5 6 7 8 9 10 11 S 1 I-1 S 2 S 3 S 4 S 5 S 6 I-1 No n-p I-1 Wa ipe I-1 ste line I-1 dc de I-2 loc xec k c ut I-2 yc ion les I-2 12 IA-32 Architecture For k stages and n instructions, the number of required cycles is: k + n – 1 I-2 I-2 Pipelined Execution COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 35
Wasted Cycles (pipelined) v When one of the stages requires two or more clock cycles to complete, clock cycles are again wasted ² Assume that stage S 4 is the execute stage Stages ² As more instructions enter the pipeline, wasted cycles occur ² For k stages, where one stage requires 2 cycles, n instructions require k + 2 n – 1 cycles IA-32 Architecture Cycles ² Assume also that S 4 requires 2 clock cycles to complete 1 2 3 4 5 6 7 8 9 10 11 S 1 I-2 I-3 S 2 I-1 I-2 I-3 COE 205 – Computer Organization and Assembly Language – KFUPM S 3 I-1 I-2 I-3 exe S 4 I-1 I-2 I-3 S 5 S 6 I-1 I-2 I-3 © Muhamed Mudawar – slide 36
Superscalar Architecture v A superscalar processor has multiple execution pipelines v The Pentium processor has two execution pipelines ² Called U and V pipes v In the following, stage S 4 has 2 pipelines ² Each pipeline still requires 2 cycles ² Second pipeline eliminates wasted cycles ² For k stages and n instructions, number of cycles = k + n IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 37
Next. . . v Basic Computer Organization v Intel Microprocessors v IA-32 Registers v Instruction Execution Cycle v IA-32 Memory Management IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 38
Modes of Operation v Real-Address mode (original mode provided by 8086) ² Only 1 MB of memory can be addressed, from 0 to FFFFF (hex) ² Programs can access any part of main memory ² MS-DOS runs in real-address mode v Protected mode (introduced with the 80386 processor) ² Each program can address a maximum of 4 GB of memory ² The operating system assigns memory to each running program ² Programs are prevented from accessing each other’s memory ² Native mode used by Windows NT, 2000, XP, and Linux v Virtual 8086 mode ² Processor runs in protected mode, and creates a virtual 8086 machine with 1 MB of address space for each running program IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 39
Real Address Mode v A program can access up to six segments at any time ² Code segment ² Stack segment ² Data segment ² Extra segments (up to 3) v Each segment is 64 KB v Logical address ² Segment = 16 bits ² Offset = 16 bits v Linear (physical) address = 20 bits IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 40
Logical to Linear Address Translation Linear address = Segment × 10 (hex) + Offset Example: segment = A 1 F 0 (hex) offset = 04 C 0 (hex) logical address = A 1 F 0: 04 C 0 (hex) what is the linear address? Solution: A 1 F 00 (add 0 to segment in hex) + 04 C 0 (offset in hex) A 23 C 0 (20 -bit linear address in hex) IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 41
Your turn. . . What linear address corresponds to logical address 028 F: 0030? Solution: 028 F 0 + 0030 = 02920 (hex) Always use hexadecimal notation for addresses What logical address corresponds to the linear address 28 F 30 h? Many different segment: offset (logical) addresses can produce the same linear address 28 F 30 h. Examples: 28 F 3: 0000, 28 F 2: 0010, 28 F 0: 0030, 28 B 0: 0430, . . . IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 42
Flat Memory Model v Modern operating systems turn segmentation off v Each program uses one 32 -bit linear address space ² Up to 232 = 4 GB of memory can be addressed ² Segment registers are defined by the operating system ² All segments are mapped to the same linear address space v In assembly language, we use. MODEL flat directive ² To indicate the Flat memory model v A linear address is also called a virtual address ² Operating system maps virtual address onto physical addresses ² Using a technique called paging IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 43
Programmer View of Flat Memory v Same base address for all segments Linear address space of ² All segments are mapped to the same linear address space a program (up to 4 GB) 32 -bit address ESI v EIP Register ² Points at next instruction 32 -bit address EIP v ESI and EDI Registers ² Contain data addresses CODE 32 -bit address ² Used also to index arrays v ESP and EBP Registers EBP CS DS SS ² EBP is used to address parameters and variables on the stack ES COE 205 – Computer Organization and Assembly Language – KFUPM STACK ESP ² ESP points at top of stack IA-32 Architecture DATA EDI Unused base address = 0 for all segments © Muhamed Mudawar – slide 44
Protected Mode Architecture v Logical address consists of ² 16 -bit segment selector (CS, SS, DS, ES, FS, GS) ² 32 -bit offset (EIP, ESP, EBP, ESI , EDI, EAX, EBX, ECX, EDX) v Segment unit translates logical address to linear address ² Using a segment descriptor table ² Linear address is 32 bits (called also a virtual address) v Paging unit translates linear address to physical address ² Using a page directory and a page table IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 45
Logical to Linear Address Translation Upper 13 bits of segment selector are used to index the descriptor table GDTR, LDTR TI = Table Indicator Select the descriptor table 0 = Global Descriptor Table 1 = Local Descriptor Table IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 46
Segment Descriptor Tables v Global descriptor table (GDT) ² Only one GDT table is provided by the operating system ² GDT table contains segment descriptors for all programs ² Also used by the operating system itself ² Table is initialized during boot up ² GDT table address is stored in the GDTR register ² Modern operating systems (Windows-XP) use one GDT table v Local descriptor table (LDT) ² Another choice is to have a unique LDT table for each program ² LDT table contains segment descriptors for only one program ² LDT table address is stored in the LDTR register IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 47
Segment Descriptor Details v Base Address ² 32 -bit number that defines the starting location of the segment ² 32 -bit Base Address + 32 -bit Offset = 32 -bit Linear Address v Segment Limit ² 20 -bit number that specifies the size of the segment ² The size is specified either in bytes or multiple of 4 KB pages ² Using 4 KB pages, segment size can range from 4 KB to 4 GB v Access Rights ² Whether the segment contains code or data ² Whether the data can be read-only or read & written ² Privilege level of the segment to protect its access IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 48
Segment Visible and Invisible Parts v Visible part = 16 -bit Segment Register ² CS, SS, DS, ES, FS, and GS are visible to the programmer v Invisible Part = Segment Descriptor (64 bits) ² Automatically loaded from the descriptor table IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 49
Paging v Paging divides the linear address space into … ² Fixed-sized blocks called pages, Intel IA-32 uses 4 KB pages v Operating system allocates main memory for pages ² Pages can be spread all over main memory ² Pages in main memory can belong to different programs ² If main memory is full then pages are stored on the hard disk v OS has a Virtual Memory Manager (VMM) ² Uses page tables to map the pages of each running program ² Manages the loading and unloading of pages v As a program is running, CPU does address translation v Page fault: issued by CPU when page is not in memory IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 50
Paging – cont’d Page m . . Page 2 Page 1 Page 0 Hard Disk Each running program has its own page table Page n Pages that cannot fit in main memory are stored on the hard disk linear virtual address space of Program 2 The operating system uses page tables to map the pages in the linear virtual address space onto main memory linear virtual address space of Program 1 Main Memory The operating system swaps pages between memory and the hard disk As a program is running, the processor translates the linear virtual addresses onto real memory (called also physical) addresses IA-32 Architecture COE 205 – Computer Organization and Assembly Language – KFUPM © Muhamed Mudawar – slide 51
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