HWSW Partitioning Embedded Systems Design 1 HardwareSoftware Codesign

HW/SW Partitioning Embedded Systems Design 1

Hardware/Software Codesign • “Exploration of the system design space formed by combinations of hardware software component” [Kaplan, Sarrafzadeh, Kastner 2003] 2

Hardware/Software Partitioning • Division of system specification into hardware and software components – What are the criteria we need to perform partitioning? 3

Partitioning • CAD optimization problem – occurs at every level of abstraction grouping of related modules to • satisfy constraints • optimize design criteria – examples • put highly connected gates in the same partition 4

Partitioning • Hierarchical model – standard cells – macro cells (logic) – blocks (architecture) 5

Partitioning • K-way partitioning problem • Evaluation is done through estimation function – take a partition (or cluster) P and returns a set of evaluated design parameters, DP • DP represents properties of the circuit such as area, power, throughput, latency, etc. – whether the constraints are met, and the system is optimized 6

So what then is HW/SW partitioning • Original goal: to find a partitioning configuration that satisfies the required performance (constraints) with minimum amount of hardware area (optimization) • Other goals – fixed hardware size (constraint) -> maximum execution performance (optimization) – fixed hardware size (constraint) -> minimum energy consumption – realtime requirement (constraint) -> minimum hardware usage (optimization) 7

HW/SW Partitioning • NP Complete – exploration of a designed space that is exponential in size • Must be done early in the design cycle – accurate estimation function is needed 8

HW/SW Partitioning • Early system – task level partitioning (coarse grain) – extracted software portions as targets for hardware realization based on three criteria • impact of partition on the overall execution time • execution time difference between hardware and software implementation of the same task • total cost of hardware 9

HW/SW Partitioning • Heuristic search approach (Gupta et al. ) – looking for satisfactory performance with minimal cost – greedy base algorithm – operation level – initial condition -> all hardware systems can satisfy the performance requirement 10

HW/SW Partitioning • Heuristic search approach – move operation out to software based on communication overhead – movements were not taken if it does not improve the cost of the system • often get stuck in local minimum -> sub-optimal partitioning • result in solutions with expensive hardware cost 11

HW/SW Partitioning • Hill climbing (Ernst et al. ) – Start with an initial partitioning that was improved in sub-sequent iterations – use simulated annealing to avoid local minimum • accept changes that increase the cost of a design, in hopes of achieving a more optimal final design • Petri Net (Vahid et al. ) 12

Software Side • Compile code to existing but not complete environment – Stub code can be used to simulate hardware interaction • Function calls that simulate non existing hardware – Calls to memory mapped I/O registers – Also work well with evolution boards • Supply by manufacturers • Incremental code written in anticipation for new hardware components – Based on known hardware specification 13

Hardware • So. C • Mapping of complex algorithms into hardware is now possible – ½ reduction in physical size = 4 times the amount of gates • 0. 35 micron to 0. 18 micron • Increasing wafer size • Silicon compilation – VHDL or Verilog • All modern processors use this approach • IP from third party vendors – Fab-less vendors (Advanced RISC Machines) 14

Dealing with Defects • Software bugs are tolerable and less costly to fix. Hardware bugs on the other hand… – Can cost hundreds of thousands in nonrecoverable cost (NRE) – Months of delay • Many start-ups went down because of this reason – Non-performing hardware • Repartitioning decision in the last minute 15

HW/SW Co-design and Coverification • Silicon compilation creates a single software database – One for describing hardware fabrication – One for controlling the hardware itself Software Development Specification Prototype Integrate and Test Hardware Development Time 16

HW/SW Co-design and Coverification • Silicon compilation creates a single software database – One for describing hardware fabrication – One for controlling the hardware itself Software Development Specification Integrate and Test Hardware Development Prototype saving 17

HW/SW Co-design and Coverification • Tools that bridge hardware and software – Co-design: develop hardware and controlling software together – Co-verification: verifying the correctness of hardware/software interface • Instruction Set Simulator • Bus functional model—translate high-level interface code to test vectors 18

Today’s Design Flow Iterate Software Process C/C++ code Stub code Object Codesign Phase Hardware Process Integrate HDL Test Vector/ Simulation Si Foundry DB Re-spin the ASIC 19

Summary • The line that separates hardware and software is blurring – The design processes can be viewed as similar – The artifacts can also be viewed as similar • Co-design and co-verification can reduce the development time/cost and promote better synchronization between software and hardware engineers. 20