HRORC HLTMeeting CERN 020605 Torsten Alt KIP Heidelberg

H-RORC HLT-Meeting CERN 02/06/05 Torsten Alt KIP Heidelberg

H-RORC n H-RORC : HLT-Read. Out-Receiver-Card n Tasks: - Receiving of the raw detector data - Injecting the data in the main memory of the hosts of the HLT framework - Online processing of the data in hardware - Sending processed data out of the HLT n Implementation: PCI card 64 bit/66 MHz with XILINX Virtex 4 and external DDR-SDRAM 02/06/05 CERN HLT-Meeting Torsten Alt KIP Heidelberg

H-RORC details n n n n Xilinx Virtex 4 LX 40 FPGA PCI interface with 64 bit up to 66 MHz – XILINX Logi. CORE 4 independent DDR-SDRAM modules with up to 1 Gb ( each module is available in 128/256/512/1024 Mb) 2 x Half CMC to interface up to two SIU/DIU cards 2 independent configuration schemes “simple configuration” with Xilinx Platform Prom “smart configuration” with Flash and CPLD “Ready for Linux” – Ethernet interface, RS 232 and Flash Tag. Net – Fast serial links to interconnect multiple RORCs 02/06/05 CERN HLT-Meeting Torsten Alt KIP Heidelberg

H-RORC blockdiagram JTAG CPLD ROM-FLASH Max. 64 MBit CMC HALF CFG-FLASH Max. 64 MBit CMC HALF XC 95144 XL DDR-SDRAM 0 DDR-SDRAM 1 DDR-SDRAM 2 DDR-SDRAM 3 Platform PROM Fast. Ethernet RS 232 PHY LXT 971 A MII: 24 Virtex 4 XC 4 VLX 40 (640) TAG-Net(LVDS) OSC Power 1 V 8 Power 2 V 5 Power 1 V 2 Power 3 V 3 89 3. 3 V PCI 66/64 02/06/05 CERN HLT-Meeting Torsten Alt KIP Heidelberg

Component layout MX XCF MT MX XC 95 MT XC 4 LX 40 MT MT PHY 02/06/05 CERN HLT-Meeting Torsten Alt KIP Heidelberg

Virtex 4 LX 40 n n n n n 41. 472 Logic Cells 288 Kb Distributed RAM ( 18. 432 x 16 bit) 1728 Kb dual-port Block RAM (96 x 18 KBit) 64 DSP slices : 18 x 18 two’s complement multiplier 48 bit accumulator & adder/subtracter 8 Digital Clock Manager (DCM) 4 Phase-Matched Clock Dividers (PMCD) 640 User I/Os Flexible I/O technology : i. e. PCI, DDR 2 partial/full reconfigurable while operating 02/06/05 CERN HLT-Meeting Torsten Alt KIP Heidelberg

“Simple configuration scheme” n n n “Simple configuration” – the Virtex 4 is configured via the Xilinx Platform PROM, a dedicated circuit for configuring Xilinx FPGAs PROM is Flash based and can be written by JTAG Virtex 4 can be configured without a PC Used for standalone mode, i. e. Labs Redundant when operated in PC/HLT 02/06/05 CERN HLT-Meeting Torsten Alt KIP Heidelberg

“Smart configuration scheme” n n n n Virtex 4 is configured out of the CFG Flash via a CPLD CFG Flash can have up to 4 independent configurations 1 Factory and 3 User configurations Factory configuration contains a small design that allows to write the user configurations over PCI and set an active flag Virtex 4 is configured with the active user configuration CPLD has internal watchdog. This watchdog can be disabled by writing a special sequence from the Virtex 4 to the CPLD to indicate a valid configuration If watchdog is not disabled within a certain time, it will assume a corrupt design in the Virtex 4 and reload the Factory configuration 02/06/05 CERN HLT-Meeting Torsten Alt KIP Heidelberg

Writing configuration XC 95144 XL FAC USR CFG FLASH USR VIRTEX 4 LX 40 PCI 02/06/05 CERN HLT-Meeting Torsten Alt KIP Heidelberg

User configuration loaded XC 95144 XL WATCHDOG FAC USR CFG FLASH USR VIRTEX 4 LX 40 PCI 02/06/05 CERN HLT-Meeting Torsten Alt KIP Heidelberg

User configuration failed XC 95144 XL WATCHDOG FAC Loading factory default FAI LED USR CFG FLASH USR VIRTEX 4 LX 40 write sequence PCI 02/06/05 CERN HLT-Meeting Torsten Alt KIP Heidelberg

User configuration succeded XC 95144 XL WATCHDOG FAC USR CFG FLASH write sequence USR VIRTEX 4 LX 40 write sequence PCI 02/06/05 CERN HLT-Meeting Torsten Alt KIP Heidelberg