HMP for Io T The path to powerful

HMP for Io. T – The path to powerful ultra-efficient nodes Mike Eftimakis Io. T Product Manager Linley Io. T Conference July 2017 © ARM 2017

Agenda 2 § What is HMP? § HMP for Io. T § System design considerations © ARM 2017

What is HMP? 3 © ARM 2017

What is HMP? CPU GPU ISP Video Interconnect Displa y Audio DSP DDR MCU A heterogeneous system using different compute elements 4 © ARM 2017 A heterogeneous subsystem using different processors cores

Why heterogeneous computing? Increase system performance Increase system efficiency “Right-sized processing” 5 © ARM 2017 Reduce system cost

Heterogeneous multicore processors Multicore Homogeneous Heterogeneous Performance asymmetry § § § Same ISA Same microarchitecture Same view of memory § § Same ISA Different microarchitecture Same view of memory OS/Software symmetry Functional asymmetry § § Different ISA Different microarchitecture Different view of memory OS/Software asymmetry Cortex-A + Cortex-M systems Interconnect 6 © ARM 2017 Interconnect

Architectural differences between Cortex families Cortex-A Cortex-R Cortex-M Higher performance Lower power, smaller area Operating System Instruction set Interrupts Bus interface 7 © ARM 2017 Rich OS/ RTOS only 32/64 b ARM and Thumb 32 b ARM and Thumb ISA 32 b Thumb ISA Deterministic SW HW managed interrupt SW managed interrupts managed AMBA AHB/AXI AMBA AXI Ideal for user interface and media processing Ideal for alwayson processing

HMP for Io. T 8 © ARM 2017

Focus on Io. T Nodes and Gateways Io. T Nodes Applications Management Sensor Actuator Small data 9 © ARM 2017 Local Gateway Global Base Station Server Big data

Characteristics of Io. T devices § Power constrained § § § Battery operation Long usage life § § § Increasing performance § § § 10 © ARM 2017 More sensors Machine learning Complex control § Security § Low cost Always ready Most of the time scanning Side applications § § Voice control Smart sensing § Security § Low cost

Why HMP for Io. T? § Need to process locally § § Other reasons § § 11 Low power High efficiency But low-cost Reuse SW ecosystem Cortex-A Rich UI Real-time control Cortex-M Context awareness © ARM 2017

Io. T systems have diverse workloads Energy Interactive mode Ambient mode • • Sensing Notifications Time / date Calendar • • Search Messages Audio / Video Calling Sleep mode Time Energy Regular sampling • • • Check environment Wait for trigger RF scanning Exception handling • • Face recognition Video streaming Time 12 © ARM 2017

18 x CPU 0 © ARM 2017 60 x More performance Cortex-A 32 13 Power Performance HMP system example Cortex-M 33 CPU 1 Less power Cortex-A 32 Top level Cortex-M 33 CPU 0 CPU 1

System design considerations 14 © ARM 2017

System design considerations § Memory map fusion – partitioning § Security § Power optimization § Inter-processor communication § Software § Debug Generic HMP compute subsystem using Cortex processors Cortex-A subsystem Interconnect DDR © ARM 2017 AHB interconnect Local memory Shared L 2 DMC 15 Cortex-M subsystem AHB interconnect Senso r Timer SRAM

Memory map fusion – subsystem partitioning § Different memory maps § § § Cortex-A – 48 bit address space Cortex-M – 32 bit Cortex-A CPU cluster AXI /AHB interconnect SMMU to virtualize Cortex-M address space § § § Run-time configuration Memory mapped dynamically Independent application space AXI interconnect Peripherals § § 16 Private – Local or shared with access controlled by SMMU © ARM 2017 Local memory and peripherals SMMU DMC § Cortex-M subsystem DDR AHB interconnect Senso r Timer SRAM

Security § Cortex-M and Cortex-A can both support Trust. Zone § Virtualizing the Cortex-M address space with SMMU § § Each subsystem address space is independent Isolation from other Cortex-M systems through the SMMU Cortex-A system can control access and sharing Trusted (secure ) Secure enclave § § 17 Non-trusted (normal) Accelerates crypto functions Hides keys from the rest of the system Form the root of Trust Handles life cycle state control and debug access control © ARM 2017 Trusted software Trusted hardware Crypto Secure system Secure storage TRNG

Power optimization § Multiple power domains § § Multiple system power state § § 18 Include hibernation when system is idle for a long time Built-in hardware based power control § § Reduce leakage current when not in use Dynamic power control with reduced SW overhead Dynamic hierarchical clock gating © ARM 2017

Inter-processor communication § Messaging § § Requirements § § § 19 Register based interrupt Shared memory for large messages Registers for small messages Split power domain Clock crossing Receiver power down state © ARM 2017

Example software concept Cortex-M Software Components Cortex-A Software Components Cloud Services Cloud client Linux Applications Cortex-M Applicatio n Provisionin g Linux TEE Secure Data U-Boot Secure processes Security Enclave 20 © ARM 2017 SMMU Secure service s Cloud client RTOS Secure processes System Platform . . MHU Secure/Non-Secure Peripherals

Example Software Concept 2 Cortex-A Software Cortex-M Software Cloud Services Cloud client Linux Applications Cortex-M Software Cortex-M Applicatio n RTOS Secure processes Linux Memory compartments configured by the pico-visor Secure Services Security Enclave 21 © ARM 2017 Pico-visor Secure processes SMMU System Platform . . MHU Secure/Non-Secure Peripherals

Debug § Merged debug access solution § § § Cross triggering and shared timestamp between all systems § Support for certificate authentication § § 22 Single Debug Access Port Access to each processor subsystem can be independently controlled Multiple Core. Sight Authentication “zones” Configurable trace support © ARM 2017

DS-MDK for Cortex-A/Cortex-M hybrid devices Debug Analyze 23 © ARM 2017 Debug Linux/RTOS apps from a single tool OS awareness Optimize

Conclusion § HMP is needed to enable more powerful Io. T systems § Tools are available to start building HMP systems now Talk to us about HMP 24 © ARM 2017

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