HIGHSPEED VLSI TESTING WITH SLOW TEST EQUIPMENT Available
HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT § Available automatic test equipment (ATE) speed is 100200 MHz; VLSI chip speed is 0. 5 -1 GHz. § Expensive to replace the existing ATE. Besides, chip speed remains an advancing target. § Existing delay test solutions insert hardware into chip • Scan method has limited path activation capability • Built-in self-test (BIST) uses random vectors that often activate non-functional paths § Problem: Develop a delay test method for slow ATEs that will give similar path coverage as obtained with an atspeed ATE • Add no test hardware to chip • Test only functional paths June 10, 2001 High-speed test 1
A NEW METHOD § Given a vector-set with specific at-speed PDF coverage, the ATE repeats the slow-speed test N times, where N is the ratio of chip-speed to the ATE-speed. § In each slow-speed vector application • Flip-flops are clocked at the rated high-speed • Output monitoring instant is advanced by an additional interval that equals rated high-speed clock period § Test application time = N Slow vector application, N=4 Vector i i+1 PI CK Rated-clock generated by pin-multiplexing June 10, 2001 2 x (test time of at-speed ATE) Sequential circuit under test (gates and flip-flops) Slow output monitoring repeated N times PO Appln. 1 Appln. 2 Appln. 3 Appln. 4 High-speed test 2
SOME RESULTS OF NEW METHOD 1. Simulated Benchmark circuits (ISCAS’ 89) Path delay fault Coverage (%) 50 40 At-speed ATE S 510 : 5, 000 random vectors S 5378 : 5, 000 random vectors Slow ATE (N=2, 3, 4) gives the same path coverage as at-speed ATE (N=1). 30 20 10 1 2 3 4 ATE slowdown factor (N) 2. A 4 MHz off-the-shelf chip tested on Agilent 82000 ATE N=1 (at-speed) N=2 (Half-speed) N=4 (1/4 speed) 4. 367 MHz 3. 937 MHz* 3. 922 MHz* * Some tested paths are longer than those tested by at-speed test. June 10, 2001 High-sped test 3
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