HighSpeed Serial Interface Test in Production Assure Device

High-Speed Serial Interface Test in Production Assure Device Interoperability In Real-World Environments

About Guide. Tech ü Specializing in Precision Timing for Semiconductor Test and Scientific Lab Communities since 1988 ü Core Technologies § Continuous Time Interval Analyzer (CTIA) § Fast Datacom Analysis Software (DCA) § High Channel Count, Parallel Architecture Targeting production test of high-speed serial interfaces

Sample Applications Semiconductor Test ü PLL & Spread Spectrum Clocks ü Source Synchronous Bus ü Embedded-Clock Serial I/O ASE test floor Scientific Analysis ü Jet Engine Rotation/Vibration ü Atomic Clock Drift & Particle decay ü Guide. Tech Keeps the Planet’s time! US Master Clock at the US Naval Observatory

The Need for Speed ü PCs move to high-speed serial buses in 20051 § 80% - 2. 5 Gbps PCI-Express § 100% - 1. 5 Gbps Serial-ATA § 20% - Gigabit Ethernet ü But test quality is not yet assured! 2 pairs of differential channels @ >800 Mbps 16 channels @ < 200 Mbps Controller Device 1 Morgan Stanley – Sep 22, 2003 Semiconductor Capital Equipment Industry Research Controller Device

ATE Performance Gap 1. 2 G - 3. 2 G Embedded-clock Serial (e. g. XAUI, SATA, FC & PCI-Express) Performance 1. 6 G Source Synchronous Flat Panel DVI Digital Video Interface Guide. Tech has been filling the gap since 2001 High Speed High Accuracy High Throughput Asynchronous test DUT 400 MHz +/-150 ps Digital Synchronous ATE Spread Spectrum PLL Clocks To lower EMI emissions of cell phones & consumer devices 2001 2004 Year

A New Test Paradigm Scope CTIA & DCA • Slow, Statistical Averaging • Gross test of Total Jitter & Eye • Fast, Frequency Domain Analysis • Per-edge timing analysis

Continuous TIA Technology ü Continuous Timestamps § Record edge timing & event count relative to (T 0, E 0) ü Multiple measurement types derived from same data set ü All measurement channels reference same (T 0, E 0) ü Powerful Pulse Selection Arming § “Walk” measurements through data patterns § Skip pulses to measure specific pulses E 0 E 1 T 0 T 1 E 2 T 3 E 3 T 4 T 5 T 6 CTIA Local Memory Meas # 1 2 3 Event # E 1 E 2 E 3 Timestamps T 1 , T 2 T 3 , T 4 T 5 , T 6 Real-Time DSP PWE 2 Meas # 1 2 3 Event # E 1 E 2 E 3 Pulse Width T 2 – T 1 T 4 – T 3 T 6 – T 5

Non-Continuous TIA Drawbacks ü Non-Continuous TIA based on simple Time Counter technology § Random, absolute measure of time intervals § No inherent reference to common (T 0, E 0) § Relies heavily on Statistical Analysis methods Time interval #1 Time Interval #2 ü Requires physical Pattern Marker for highest accuracy § Pattern match adds test time to synchronize to patterns § Pattern match unreliable in presence of large jitter ü Requires repeating SEARCH for one-shot measurements § PLL Lock Time

CTIA Single-Shot Capability ü Test PLL & Spread Spectrum Clocks in production ü One-shot § Frequency § Modulation § Lock Time § Jitter ü No arming ü Picosecond accuracy ü In milliseconds ü 8 in parallel ü Up to 64 channels

CTIA Frequency Domain Analysis ü CTIA time correlation enables plot of time interval error (TIE) Dt 0 TIE Dt Dt 1 Dt 2 (ps) Dt 3 Dt 4 Dt 5 Dt 6 Auto Correlation Plot Of Sinusoidal Jitter Time (us) FFT of the TIE plot provides the amplitude and frequency of sinusoidal jitter/modulation AMPLITUDE fjitter FREQ

Functional Test of Non-deterministic Signals ATE Digital Compare Method – Requires Match Mode to position strobes 11 00 1 0 0 1 0 0 Match 1 1 0 0 1 0 0 Non-continuous TIA – Requires Marker to locate desired bit location 11 00 1 0 0 11 Pattern Marker 11 00 1 0 0 Match 00 1 0 0 11 00 1 0 0 PM selects the next desired pulse to measure Continuous TIA – Reconstructs repeating signals with ‘Virtual Marker’ 11 GT 4000 T 0 E 0 00 1 0 0 11 T 1 E 2 00 1 0 0 11 T 2 E 5 00 1 0 0 11 T 3 E 7 00 1 0 0

CTIA “Virtual Marker” ü Edge isolation & reconstruction of non-deterministic bit patterns § Known Bit Pattern & UI § Selectable Bit Event Count § Correlated CTIA Timestamps (Tn, En) ü More reliable than a physical pattern marker in high jitter signals ü Reduces test times to milliseconds for… § Per-edge jitter analysis § Asynchronous pattern verification

Serial Interface Test in Production ü Many test options § § High-$peed ATE BERT Scope Jitter Analyzers ü Few cost-effective approaches § Loopback § On-chip DFT/BIST But ‘no test’ is not an option anymore…

Serial I/O Loopback Test ü Benefits § Low-cost vs expensive ATE pin electronics § Addresses asynchronous issue with ATE TXdiff RXdiff ü Drawbacks § Gross Functional Test only § Does not insure device interoperability in real-world system environments

Assure Real-World Performance ü BER helps insure real-world performance but is too slow for production ü High-throughput jitter analysis can estimate BER in production Far-end Near-end § TX Jitter Analysis • Predicts far-end jitter degradation after TX signal is subjected to system connectors, switches and PCB traces TXdiff CTIA measures TX jitter in loopback path RXdiff

Random Jitter ü Causes of Random Jitter § Thermal noise § Transistor current fluctuation ‘shot’ noise § Flicker noise (1/f noise) ü Random Jitter is a contributing factor to Bit Error Rate BER 10 -6 10 -8 SJ DJ 10 -10 Qx. RJ Eye Width @ BER 10 -12 Q = 14. 069 @ BER 10 -12

RJ is important for fast BER estimation ü Measuring Bit Error Rate on a BERT can take hours or days ü Quickly determine Total Jitter for a BER of 10 -12 BER Jitterp-p = ( Q x RJRMS ) + DJ Q = 14. 069 @ BER 10 -12 Qx. RJ ü Due to the large Q multiplication factor, RJ measurements must not be contaminated by PJ and DDJ components Probability Density Functions (PDF) of jittering edge timing Gaussian RJ RJ contaminated by PJ RJ contaminated by DDJ

Data-Dependent Jitter is Important ü Most PHY-layer I/O failures are DDJ-related ü Causes of DDJ § Bandwidth limitations in signal path • Frequency dependent • Pattern dependent § Output driver faults § Duty cycle distortion § Rise/fall times § Packaging

CTIA Data. Com Jitter Analysis q Guide. Tech DCA Provides: ü Data Pattern Verification ü Random Jitter (RJ) ü Data-Dependent Jitter (DDJ) ü Periodic Jitter (PJ) ü Total Jitter (TJ) ü Bit Error Rate (BER) ü Eye Width Continuous TIA technology enables fast and accurate quality assurance

CTIA RJ Immune to PJ ü CTIA continuous timestamping enables ü Statistical (Curve fit) methods are prone to isolation of the RJ noise floor by removal of estimation errors depending on the PDF PJ frequency components in the FFT shape spectrum and DDJ using virtual marker Jitter Amplitude (UI) Remove Spread Spectrum Clock Modulation 1 UI Remove other periodic jitter 0. 5 UI Remaining Noise Floor (Random RMS Jitter) 0. 1 UI 0. 1 MHz 10 MHz 50 MHz PDF showing RJ contaminated by PJ & DDJ

RJ Immunity to DDJ ü CTIA continuous timestamps act as a ‘virtual’ marker § Isolate edges § Remove DDJ offset before performing FFT for RJ analysis 0101 100000100 T 0 IDEAL Edge-6 location Count DDJ offset 1 P 1 N 2 P 2 N 3 P 3 N

CTIA vs. ‘double-delta’ method ü CTIA measures edge shifts independently on each data bit § Produces highly repeatable DDJ results per-edge § Avoids inaccuracies of statistical double-delta methods* P 1 N 1 P 2 N 2 P 3 N 3 P 4 N 4 P 5 N 5 P 6 N 6 Continuous TIA Non-Continuous TIA Inherent DDJ inaccuracies of double-delta method* *Reference: Fibre Channel MJS document Section 12. 2. 2 & 12. 2. 7

10 x Throughput with Picosecond DCA Correlation to Scope ü DCA correlates to Agilent 86100 within picoseconds ü DCA test time is less than 1 sec vs. 10 sec on scope (K 28. 5)

DCA Fast Jitter Separation ü Select DCA test time § § Pattern length PJ resolution PJ ON/OFF RJ precision Test PCI Express in 1 second (including pattern verify) Test Time (sec) PJ – ON (RJ, DDJ, PJ, TJ) } PJ resolution } RJ precision 10 s 5 s 1 s PJ – OFF (RJ, DDJ & TJ only) 250 ms K 28. 5 PCIe 640 bit Compliance Pattern PRBS 15 32, 767 bits Pattern Length (bits)

The Value of Jitter Test ü Jitter test saves money § Test Escapes • Field Returns • RMA failure analysis • Lost Business § Yield Loss • Failing good devices § Time-to-Market Delays • Long characterization-to-production correlation time • Unprepared to debug unexpected process variation at final test

CTIA Provides the Missing Pieces ü Test Asynchronous signals ü High Throughput “Virtual Marker” ü Repeatable Jitter Analysis ü 64 Single-ended / 32 Differential Introducing the GT 4000 Continuous TIA Booth # 1420

High-Speed Serial Interface Test in Production Assure Device Interoperability In Real-World Environments 2004