High Precision Timing Distribution Interest Group Meeting 6
High Precision Timing Distribution Interest Group Meeting #6 Evaluation of Silicon Labs (Si 5344) PLL with Connor Winfield OCXO Mark Taylor On behalf of the HPTD team (E. Mendes, M. Taylor, S. Baron) 24/09/2019 mark. norman. taylor@cern. ch 1
Outline • Objectives • Methodology • Standalone OCXO • Si 5344 Freerun • Si 5344 Locked • Conclusions 24/09/2019 mark. norman. taylor@cern. ch 2
Objectives • Comparisons with other generator sources: • 40 MHz RF Bunch Clocks at SR 4 • Stanford Research Systems Model CG 635 2. 05 GHz Synthesized Clock Generator • Evaluate performance of Silicon Labs Si 5344 -EB REV 3. 0 (B) PLL with: • Si 5344’s on-board 48 MHz XTAL • Connor-Winfield Corp OH 300 50 MHz SC-cut OCXO on Timing Evaluation Board via SMA • Prototype of low-cost custom HPTC board for high-precision timing evaluation Si 5344 OCXO 10 cm 24/09/2019 Si 5344 + OCXO mark. norman. taylor@cern. ch Custom HPTC Board 3
Methodology • Phase noise measurements using Rohde & Schwarz FSWP 8 Phase Noise Analyzer • rms phase jitter values integrated from 1 Hz to 10 MHz • Automated scripts using a Python library developed by the HPTD team, available in the timing lab at disposal of users • Two power supplies tested: • Gossen Konstanter LSP 33 K 7 EU 5/2 X 25 RR 1 D • Aim-TTi PL 303 QMD-P Quad-Mode Dual Power Supply • Measurements repeated with two identical OCXOs: OCXO & OCXO 2 Rohde & Schwarz FSWP 8 24/09/2019 CG 635 Clock Generator Gossen Konstanter LSP mark. norman. taylor@cern. ch Aim-TTi PL 303 QMD 4
Standalone OCXO Power Supply Comparison • Gossen Konstanter LSP presents better phase-noise performance • Better DC smoothing • Lower jitter overall • OCXO evaluation board initially draws 0. 84 A, settles at ≈ 0. 3 A after 10 minutes power supplies OCXO oven control loop? OCXO generator measurement setup 24/09/2019 mark. norman. taylor@cern. ch 5
Standalone OCXO vs CG 635 • Slight variance between OCXOs • Greater sample size needed • Lower phase-noise than CG 635 for all frequency offsets CG 635 generator measurement setup 24/09/2019 mark. norman. taylor@cern. ch 6
Si 5344 Freerun XTAL vs OCXO • OCXO SC-cut close-in phase noise • 2 orders of magnitude lower total integrated phase noise OCXO Si 5344 freerun measurement setup 24/09/2019 mark. norman. taylor@cern. ch 7
Si 5344 Freerun OCXO vs RF • Comparable with current RF • Lower total integrated phase noise • Custom board improvements 24/09/2019 mark. norman. taylor@cern. ch 8
Si 5344 Locked to CG 635 with ZDM No ZDM With ZDM Si 5344 OCXO CG 635 measurement setups 24/09/2019 mark. norman. taylor@cern. ch 9
Conclusions • • • OCXO + Si 5344 PLL produces excellent clock generator Appropriate power supply needed to power OCXO Current draw is initially 0. 84 A, settles at ≈ 0. 3 A after a ≈ 10 minutes Larger sample size needed to determine variance between OCXOs OCXO + Si 5344 PLL not so advantageous over XTAL in locked mode ∴ Si 5344 PLL with an OCXO are excellent candidates for a custom board for highprecision timing evaluation. Low expected cost. Full report: Short-term clock quality of Silicon Labs PLL (Si 5344) with OCXO 24/09/2019 mark. norman. taylor@cern. ch 10
Thank You 24/09/2019 mark. norman. taylor@cern. ch 11
Spare Slides 24/09/2019 mark. norman. taylor@cern. ch 12
OCXO Modification • Si 5344 evaluation board was modified to accommodate an external reference clock via SMA connectors instead of its internal XTAL • XTAL was desoldered, R 146 and R 149 were replaced with 453 Ω resistors, R 144 was removed, C 93 and C 94 were populated with 100 n. F capacitors, and J 25 was grounded (see fig. below) • Recommended to add a capacitor in parallel with R 146 to decrease rise time (custom HPTC board improvement) External Reference Input Circuit Diagrams 24/09/2019 mark. norman. taylor@cern. ch 13
Si 5344 No ZDM vs ZDM • Lower phase noise with ZDM at frequency offset of 100 Hz for bandwidths of 100/400 Hz. Not for 1000/4000 Hz • Optimal PLL bandwidth around 1000 Hz 24/09/2019 mark. norman. taylor@cern. ch 14
Texas Instruments LMK 04832 CG 635 input freq. Set to PLL 1 CLKin. X Adjust to keep within spec TICS Pro - PLL 1 and 2 Configuration 24/09/2019 mark. norman. taylor@cern. ch 15
Minnesota OCXO - Roger Rusack 24/09/2019 mark. norman. taylor@cern. ch 16
Minnesota OCXO - Roger Rusack 24/09/2019 mark. norman. taylor@cern. ch 17
Minnesota OCXO - Roger Rusack 24/09/2019 mark. norman. taylor@cern. ch 18
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