High Current Density and High Power Density Operation
- Slides: 30
High Current Density and High Power Density Operation of Ultra High Speed In. P DHBTs Mattias Dahlström 1, Zach Griffith, Young-Min Kim 2, Mark J. W. Rodwell Department of ECE University of California, Santa Barbara, USA (1) Now with IBM Microelectronics, Essex Junction, VT (2) Now with Sandia National Labs, NM mattias@ece. ucsb. edu 805 -893 -8044, 805 -893 -3262 fax
Overview • Fast devices and circuits need high current! – Current limited by • Kirk current threshold • Device heating – Thermal resistance Device heating • Design of low thermal resistance HBT • High Current Devices with state of the art RF performance
The need for high current density Scaling laws: Single HBT: f Je=8 m. A/ m 2 Digital circuit Key performance parameters: Je=6. 9 m. A/ m 2 Minimize capacitance charging times! Increase current density Output spectrum @ 59. 35 GHz, fclk=118. 70 GHz
Thermal conductivity of common materials Ternaries lattice matched to In. P
HBT: Where is the heat generated? Vbe = 0. 95 V, Vce = 1. 3 V Power generation: JE x VCE=6 x 1. 5 V=9 m. W/ m 2 In the intrinsic collector
HBT: heat transport Thermal resistance of materials in collector and subcollector critical Main heat transport is through the subcollector to the substrate Up to 30 % heat transport up through the emitter contact
How to design a low thermal resistance HBT A five step process Identify high thermal resistance materials change them low thermal resistance materials Very simple!
SHBT: In. Ga. As collector Design of low thermal resistance HBT: Initial design: In. Ga. As collector
SHBT: In. Ga. As collector, In. P emitter Design of low thermal resistance HBT: Emitter: In. Al. As In. P
DHBT: In. Ga. As/In. P collector Design of low thermal resistance HBT: In. Ga. As collector In. P collector with In. Ga. Al. As grade
DHBT: In. Ga. As/In. P collector, In. Ga. As/In. P subcollector Design of low thermal resistance HBT: In. Ga. As subcollector In. Ga. As/In. P composite subcollector
DHBT: In. Ga. As/In. P collector, thin In. Ga. As/In. P subcollector Design of low thermal resistance HBT: Thick In. Ga. As in subcollector thin In. Ga. As in subcollector
Metamorphic-DHBT: In. Ga. As/In. P collector, In. Ga. As/In. P subcollector Young-Min Kim Design of low thermal resistance Metamorphic HBT: In. Al. As, In. Al. P, In. Ga. As buffers In. P buffer
Experimental Measurement of Temperature Rise Temperature rise can be calculated by measuring IC, VCE and DVBE No thermal instability as long as slope<∞ each VBE gives a unique IC
Thermoelectric feedback coefficient (data from W. Liu) W. Liu: “Thermal Coupling in 2 -Finger Heterojunction Bipolar Transistors” , IEEE Transactions on Electron Devices, Vol 42 No 6, June 1995 W. Liu: H-F. Chau, E. Beam, "Thermal properties and Thermal Instabilities of In. P-Based Heterojunction Bipolar Transistors”, IEEE Transactions on Electron Devices, Vol 43 No 3, March 1996 Thermoelectric feedback coefficient for Al. Ga. As/Ga. As HBTs 4 % smaller Not a large influence from material or structure variations
High f DHBT Layer Structure and Band Diagram In. Ga. As 3 E 19 Si 400 Å In. P 3 E 19 Si 800 Å Vbe = 0. 75 V, Vce = 1. 3 V Emitt er In. P 8 E 17 Si 100 Å In. P 3 E 17 Si 300 Å In. Ga. As 8 E 19 5 E 19 C 300 Å Setback 3 E 16 Si 200 Å Bas e Collect or Grade 3 E 16 Si 240 Å In. P 3 E 18 Si 30 Å In. P 3 E 16 Si 1030 Å In. P 1. 5 E 19 Si 500 Å In. Ga. As 2 E 19 Si 125 Å In. P 3 E 19 Si 3000 Å SI-In. P substrate Compared to previous UCSB mesa HBT results: • Thinner In. P collector—decrease c • Collector doping increased—increase JKirk • Thinner In. Ga. As in subcollector—remove heat • Thicker In. P subcollector—decrease Rc, sheet
Thermal resistance results: lattice matched 25 nm In. Ga. As Measured thermal resistances for lattice matched HBTs. Ic= 5 m. A, Vce=1. 5 V, P=7. 5 m. W 12. 5 nm In. Ga. As Device Buffer (mm) Tc (nm) Tsc In. Ga. As (nm) Tsc In. P (nm) JA K/m. W DHBT M 1 200 25 125 2. 5 DHBT 19 b 150 12. 5 300 1. 8 DHBT 23 150 12. 5 300 1. 4 50 nm In. Ga. As 25 nm In. Ga. As: large improvement
Thermal resistance results: metamorphic 50 nm In. Ga. As In. Al. P buffer Measured thermal resistances for metamorphic HBTs. Ic= 5 m. A, Vce=1. 5 V, P=7. 5 m. W 25 nm In. Ga. As In. P buffer Device Buffer (mm) Tc (nm) Tsc In. Ga. As (nm) Tsc In. P (nm) JA K/m. W M HBT 1 In. Al. P 1. 5 200 50 125 7. 6 M HBT 2 In. P 1. 5 200 50 125 3. 3 M HBT 11 In. P 1. 5 200 25 300 3. 1 In. Al. P In. P buffer: large improvement 50 nm In. Ga. As 25 nm In. Ga. As: small improvement
Device and circuit results Transistor operation at 13 m. A/ m 2 150 nm In. Ga. As/In. P collector 370 GHz ft at Jc>8 m. A/ m 2 Zach Griffith 28 transistor static frequency divider @ fclk=118. 7 GHz shown To be reported, 150 GHz static divider using same Type 1 DHBT structure—chirped Continuous superlatticeoperation at high current densities greater than peak rf performance (Je = 8 m. A/ m 2)
Our Mesa DHBTs have Safe Operating Area Extending beyond High-Speed Logic Bias Conditions Low-current breakdown is > 6 Volts this has little bearing on circuit design Safe operating area is > 10 m. W/um 2 these HBTs can be biased. . at ECL voltages. . . while carrying the high current densities needed for high speed
Conclusions • DHBT design with In. P subcollector very low thermal resistance • Metamorphic DHBT with In. P buffer low thermal resistance • DHBT operation at Jc>13 m. A/ m 2 • Optimal device and circuit performance at Jc up to 8 m. A/ m 2 • HBT I-V operating area allows static frequency dividers operating at speeds over 150 GHz
Backup slides
HBT
Why is thermal management important? • As J increases so does the power density. This will lead to an increase in the temperature. TC JKirk Le Å m. Aμm-2 μm 3000 1. 0 81 2000 2. 3 34 1500 4. 1 19 1000 9. 8 8. 6 For VCE=1 V PD=10. 6 m. Wμm-3 For VCE=1 V PD=98 m. Wμm-3!!
Thermal Modeling of HBT (1) • 3 D Finite Element using Ansys 5. 7 • K (Thermal conductivity) depends temperature • K depends on doping • For Ga. As heavily doped Ga. As 65% less than undoped Ga. As • Unknown for In. P or In. Ga. As use Ga. As dependency Material K 300 n K 300(exp) Refs In. P 0. 68 1. 42 0. 68 -0. 877 1 In. Ga. As 0. 048 1. 375 0. 048 -0. 061 2 Au 3. 17 - Large uncertainty in values 3 J. C. Brice in “Properties of Indium phosphide” eds S Adachi and J. Brice pubs INSPEC London p 20 -21 S Adachi in “Properties of Latticed –Matched and strained Indium Gallium Arsenide” ed P Bhattacharya pubs INSPEC London p 34 -39 “CRC Materials science and engineering handbook”, 2 nd edition , eds J. F Shackelford, A. Alexander, and J. S Park, pubs CRC press, Boca Raton, p 270
Validation of Model Caused by Low K of In. Ga. As Ian Harrison Max T in Collector Ave Tj (Base-Emitter) =26. 20°C Measured Tj=26°C Good agreement. Advice Limit In. Ga. As Increase size of emitter arm
Analysis of 40, 80, 160 Gbit/s devices Ian Harrison • To obtain speed inprovements require to scale other device parameters Speed . (Gbit/s) 40 80 160 Collector Thickness (Å) 3000 2000 1000 Base Sheet resistance ( ) 750 700 Base contact resistance ( - m 2) 150 20 10 Base Thickness (Å) 400 300 250 Base Mesa width ( m) 3 1. 6 0. 4 Current Density (m. A/ m 2) 1 2. 3 9. 8 Emitter. Junction Width ( m) 1 0. 8 0. 2 Emitter Parasitic resistivity ( - m 2) 50 20 5 Emitter Length ( m) 6 3. 3 3. 2 Predicted MS-DFF (GHz) 62 125 237 Ft (GHz) 170 260 500 Fmax (GHz) 170 440 1000 Tj (K) 7. 5 14 28 TMax (K) 10 20 49 TMax (No Etch Stop layer) (K) 7. 5 13 21 Device parameters after Rodwell et al Reduction of parasitic CBC Conservative 1. 5 x bit rate When not switching values will double
Mesa DHBT with 0. 6 m emitter width, 0. 5 m base contact width Z. Griffith, M Dahlström
How we measure thermal resistance
Layout improvement: Emitter heat sinking Improved emitter heatsinking Emitter interconnect metal 2 μm to 7 μm ~30 % of heat out through emitter Negligible increase in Cbe
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