HEPIX Technology Watch Working Group Michele Michelotto Challenges

HEPIX Technology Watch Working Group Michele Michelotto

Challenges • LHC Run 4 / phase II and other Big Sciences • Understanding better where technology and markets go becomes indispensable • Wide area of topics to be covered in a regular and systematic manner 2

WG Launch, Target, Scope • Working group launched late summer 2019 – Surprisingly high level of interest – 59 subscribers on the mailing list hepix-techwatch-wg at hepix dot org • Target: HEP experiments, in particular LHC – other communities as they collaborate in and contribute to the WG • Scope: Evolution of technology and markets – Does not include benchmarking, cost modelling, software techniques and products – covered elsewhere 3

Tech. Watch WG Organisation Chairs: Helge Meinhard, Bernd Panzer-Steindel Six sub-groups (with conveners): • General market trends, semiconductor markets, unit sales: Servesh Muralidharan, Peter Wegner; Rolf Seuster, Kai Leffhalm, Charles Leggett, Gang Chen • CPUs and accelerators: Andrea Sciaba, Eric Yen; Michele Michelotto, Rolf Seuster, Servesh Muralidharan, Domenico Giordano, Niko Neufeld, Charles Leggett, Peter Wegner, Mathieu Puel, Romain Wartel, Andrea Chierici, Andrea Valassi, Shigeki Misawa, Felice Pantaleo, Chris Hollowell, Tristan Suerink • Server markets: Chris Hollowell, Michele Michelotto; Servesh Muralidharan, Peter Wegner, Mathieu Puel, Andrea Chierici, Harvey Newman • Memories: Shigeki Misawa; Servesh Muralidharan, Andrea Sciaba, Loic Tortay, Fabio Hernandez • Storage: German Cancio, Martin Gasthuber; Federico Calzolari, Peter Wienemann, Oliver Freyermuth, Julien Leduc, Vladimir Sapunenko, Kai Leffhalm, Alessandro Brunengo, Shkelzen Rudovac, Loic Tortay, Fabio Hernandez, Eric Yen, Harvey Newman, Shigeki Misawa, Jan Erik Sundermann • Network: Edoardo Martelli, Rolf Seuster; Federico Calzolari, Fazhi Qi, Alessandro Brunengo, Harvey Newman, Tristan Suerink 4

HEPi. X Tech. Watch WG: Server Chris Hollowell, Brookhaven National Laboratory Michele Michelotto, Università e INFN, Padova (IT) On behalf of the HEPi. X Technology Watch Server Market Subgroup HOW Workshop 18 -22 March 2019 Jefferson Lab, Newport News

Server Market Global server market revenue up substantially ● $23. 37 billion in Q 3 2018 with 3. 16 million servers shipped ● Primarily due to hyperscale cloud provider purchases ● May grow to $100 billion/year industry Revenue outpacing units sold ● Increased cost of components including CPU, GPUs/FPGAs, memory and solid state storage Total server shipments per quarter now almost double what they were for an entire year ~20 years ago (1997) ● Vast majority of revenue from x 86 servers ● Other server platforms only sold $1. 6 billion in Q 3 2018: ~6. 8% New ARM Neoverse server CPU platform hopes to change the downward trend for non-x 86 servers

Server Market (Cont. ) ODMs (Original Design Manufacturers) combined have a larger server sales revenue than any single tier one vendor These servers are often purchased by hyperscale cloud providers Some examples ODMs include Foxconn, Quanta, and Inventec Approximately one in four servers shipped now going to hyperscale cloud providers Dell, HPE and Lenovo, respectively, leading tier one server vendors in terms of sales revenue AMD-based server shipments still a small portion of the total market However was 0% prior to EPYC Naples’ release AMD anticipates capturing additional server market share after the 2019 release of EPYC Rome CPUs Hyperscale cloud providers currently most heavily driving AMD server sales

Server Market - Environment and Cooling Data centers used ~3% of the world’s total electricity output in 2017 Estimated to jump to ~20% by 2025 US Do. E recommending EPEAT environmental certification for servers ”Electronic Product Environmental Assessment Tool” https: //greenelectronicscouncil. org/epeat-overview/ Both Dell and HP participating in the program, among others Rates products on 51 environmental criteria, including recycled content, toxin reduction, energy efficiency, etc. Traditionally, there’s been reluctance and little need for data centers to adopt liquid cooling technologies, although they’re considerably more efficient than air-based cooling Impediments for adoption including cost and increased maintenance complexity However, expect to see more demand for both rear-door heat-exchange and direct liquid cooling in 2019 High demand for co-processors (GPU, FPGAs, etc. ) increasing the power density of servers Increasing use of “hyperconverged infrastructure” - combining separate network, compute and storage elements into a single higher-density systems

Cooling ● ● ● Common density 10 -12 k. W/rack max to 12 -20 k. W/rack Today a 42 U rack full of 2 S nodes (80 server) can draw 40 k. W Full air cooling is not enough

Liquid Cooling Landscape Close Coupled Cooling ● In-Row, In-Rack, Rear Door Exchangers Close Coupled Cooling ● Air is still the only mean to cool board/chip ● Limited by existing chip maximum temps ● Requires additional fans DLC (Cold Plates) ● Positive Pressure, Negative Pressure Cold Plates ● Individual Heatsinks ● Board-Specific ● Individual Chip Fluid-cooling Immersion Cooling ● Single Phase, Two-Phase Immersion ● Specialty fluids ($$$) ● Can require separate cooling coil ● Orientation sensitive

Open 19 ● ● Aims at support data center design, open, economical and customizable Similar to Facebook OCP Open Compute Project that is more addressed to major internet companies Open 19 focused on optimizing data center of any size including small edge platforms, unlike OCP Define a common, open standard server form factor, using rack, cages and pre-defined network and power

Open 19 ● ● ● ● Standard 19” 4 -post rack, Brick cage Brick (B), Double Wide Brick (DWB), Double High Brick (DHB), Double High & Wide Brick (DHWB) Power shelf: 12 v distribution, OTS power modules with any AC or DC inputs Optional Battery Backup Unit (BBU) Networking switch (To. R) Snap-on power cables – up to 400 w per brick, linear growth with size Snap-on data cables – up to 100 G per brick, linear growth with size

Open Computing Project ● ● Server compute node designs included one for Intel processors and one for AMD processors. In 2013, Calxeda contributed a design with ARM processors Several subprojects: ○ ○ ○ HPC: heterogeneous computing networking and fabric platform for multi-node processor Networking: Network hardware and software Rack and Tower: rack standards, integrating the DC infrastructure Open System Firmware: OS Hw platform initialization Data Center Facility: maximizes mechanical performance and thermal and electrical efficiency Right - Open Compute V 2 Server Left - Open Compute V 2 Drive Tray, 2 nd lower tray extended

CPUs, GPUs, accelerators and memory Andrea Chierici On behalf of the Technology Watch WG

Introduction • The goal of the presentation is to give a broad overview of the status and prospects of compute technologies – Intentionally, with a HEP computing bias • Focus on processors and accelerators and volatile memory • The wider purpose of the working group is to provide information that can be used to optimize investments – Market trends, price evolution • More detailed information is already available in a document – Soon to be added to the WG website 28/03/2019 15

Outline • • General market trends CPUs and accelerators Memory technologies Supporting technologies 28/03/2019 16

GENERAL MARKET TRENDS 28/03/2019 17

Semiconductor device market and trends • Global demand for semiconductors topped 1 trillion units shipped for the first time • Global semiconductor sales got off to a slow start in 2019, as year-to-year sales decreased • Long-term outlook remains promising, due to the ever-increasing semiconductor content in a range of consumer products • Strongest unit growth rates foreseen for components of – smartphones – automotive electronics systems – devices for deep learning applications 28/03/2019 18

Semiconductor fabrication • Taiwan leading all regions/countries in wafer capacity • TSMC held 67% of Taiwan’s capacity and is leading • Samsung and SK Hynix represent 94% of the installed IC wafer capacity in South Korea – They are likely to influence memory prices (which are now very high but dropping in 2019) • New manufacturing lines are expected to boost industry capacity by 8% in both 2018 and 2019 28/03/2019 19

Process technology • Performance scaling in process technology continues to grow Moore’s law prediction • Embedded processors benefit the most from process manufacturing improvements • EUV (Extreme Ultra-Violet) is forecast to be the dominant lithography technology in the coming years – Already used for 7 nm by TSMC for AMD, Apple, Nvidia and Qualcomm 28/03/2019 20

Intel and AMD market share • AMD server market share is rapidly increasing since 2017, but from almost nothing – Zen architecture released in 2017 – Achieved 5% of server shipment market share on Q 4 2018, projected to 10% in one year Source: Passmark website (statistics are voluntarily submitted benchmark results) • AMD always had a reasonable (20 -30%) share overall • EPYC revenue was $58 m in the second 2018 quarter vs $36 m in the prior quarter 28/03/2019 21

CPUS AND ACCELERATORS 28/03/2019 23

Intel server CPU line-up • • DLBOOST (Deep Learning Boost) Feature to accelerate AI workloads: AVX-512 Vector Neural Network Instructions Brain Floating Point format (like a SP FP with a truncated mantissa field float 16: (range ~5. 96 e-8 to 65, 504) bfloat 16: (range ~1 e-38 to ~3 e 38) Intel Xeon Scalable Processors – Currently based on Skylake-SP and coming in four flavours, up to 28 cores • Only minor improvements foreseen for 2019 – Adding support for Optane DC Persistent Memory and hardware security patches • New microarchitecture (Sunny Cove) to become available late 2019 – Several improvements benefiting both generic and specialised applications 28/03/2019 24

Current and future Intel server architectures Microarchitecture Technology Launch year Highlights Skylake-SP 14 nm 2017 Improved frontend and execution units More load/store bandwidth Improved hyperthreading AVX-512 Cascade Lake 14 nm++ 2019 Vector Neural Network Instructions (VNNI) to improve inference performance Support 3 D XPoint-based memory modules and Optane DC Security mitigations Cooper Lake 14 nm++ 2020 bfloat 16 (brain floating point format) Sunny Cove (aka Ice Lake) 10 nm+ 2019 Single threaded performance New instructions Improved scalability Larger L 1, L 2, μop caches and 2 nd level TLB More execution ports Willow Cove 10 nm 2020? Cache redesign New transistor optimization Security Features Golden Cove 7/10 nm? 2021? Single threaded performance AI Performance Networking/5 G Performance Security Features 28/03/2019 25

Other Intel x 86 architectures • Xeon Phi – Features 4 -way hyperthreading and AVX-512 support – Elicited a lot of interest in the HEP community and for deep learning applications – Announced to be discontinued in summer 2018 • Networking processors (Xeon D) – So. C design – Used to accelerate networking functionality or to process encrypted data streams – Two families, D-500 for networking and D-100 for higher performance, based on Skylake -SP with on-package chipset – Hewitt Lake just announced, probably based on Cascade Lake • Hybrid CPUs – Will be enabled by Foveros, the 3 D chip stacking technology recently demonstrated 28/03/2019 26

AMD server CPU line-up • EPYC 7000 line-up from 2017 – Resurgence after many years of Bulldozer CPUs thanks to the Zen microarchitecture – +40% in IPC, almost on par with Intel – 2 x power efficiency vs Piledriver – Up to 32 cores • Already being tested and used at some WLCG sites 28/03/2019 27

EPYC Naples • EPYC Naples (Zen) consists of up to 4 separate dies, interconnected via Infinity Fabric – Chiplets allow a significant reduction in cost and higher yield • Main specifications – up to 32 cores – 4 dies per chip (14 nm), each die embedding IO and memory controllers – 2. 0 -3. 1 GHz of base frequency – 8 DDR 4 memory channels with hardware encryption – up to 128 PCI gen 3 lanes per processor (64 in dual) – TDP range: 120 W-200 W • Similar per-core and per-GHz HS 06 performance to Xeon 28/03/2019 28

EPYC Rome • Next AMD EPYC generation (Zen 2), embeds 9 dies, including one for I/O and memory access – Should compete with Ice Lake • Main specs: – 9 dies per chip : a 14 nm single IO/memory die and 8 CPU 7 nm chiplets • +300 -400 MHz for low core count CPUs 8 DDR 4 memory channels, up to 3200 MHz up to 64 cores up to 128 PCI Gen 3/4 lanes per processor TDP range: 120 W-225 W (max 190 W for SP 3 socket compatibility) – Claimed +20% performance per-core over Zen, +75% through the whole chip with similar TDP over Naples – To be released during 2019 – – 28/03/2019 29

ARM in the data center • ARM is ubiquitous in the mobile and embedded CPU world • Data center implementations have been relatively unsuccessful so far – Performance/power and performance/$ not competitive with Intel and AMD • LHC experiments can use ARM CPUs if needed – Some do nightly build on ARM since years • Only a few implementations (potentially) relevant to the data center – – Cavium Thunder. X 2 Fujitsu A 64 FX ARM Neoverse Ampere e. MAG, Graviton 28/03/2019 31

Marvell Thunder. X 2 and Fujitsu A 64 FX • Thunder. X 2 for mainstream cloud and HPC data centers, from 2018 – Enjoys the greatest market visibility and reasonable performance/$ • Used e. g. at CRAY XC-50 at Los Alamos and HPE Apollo 70 based Astra HPC system at Sandia National Laboratory – ARM V 8. 1 architecture • Up to 32 cores, 4 -way SMT • Up to 8 DDR 4 memory channels • Up to 56 PCIe Gen 3 lanes • Fujitsu A 64 FX to be used in supercomputer at RIKEN center – Based on the V 8. 2 -A ISA architecture • • First to deliver scalable vector extensions (SVE) 48 cores 32 GB of HBM 2 high bandwidth memory 7 nm Fin. FET process – Interesting to see what performance will achieve as it may lead to a more competitive product 28/03/2019 32

ARM Neoverse • Two platforms for the data center – N 1 for cloud, E 1 for throughput • Based on the Neoverse N 1 CPU – Very similar architecture to Cortex A 76 but optimized for high clock speeds (up to 3. 1 GHz) – Two N 1 cores each with L 1 and L 2 caches – To be combined by licensees with memory controller, interconnect and I/O IP • Demonstrated the N 1 Hyperscale Reference Design – – 64 -128 N 1 CPUs each with 1 MB of private L 2 8 x 8 mesh interconnect with 64 -128 MB of shared cache 128 x PCIe/CCIX lanes 8 x DDR 4 memory channels • Intended to strengthen ARM’s server market share – Not expected to be available for another 1 -1. 5 years 28/03/2019 Source: Anandtech 33

IBM POWER • POWER 9 – – – Used in Summit, the fastest supercomputer 4 GHz Available with 4 -way (up to 24 cores) First supporting PCIe-Gen 4 CAPI 2. 0 I/O to enable • Coherent user-level access to accelerators and I/O devices • Access to advanced memories – NVLink to increase bandwidth to Nvidia GPUs – 14 nm FINFET process – Product line with full support for RHEL/CENTOS 7 • POWER 10 – 10 nm process – Several feature enhancements – First to support PCIe Gen 5 28/03/2019 34

RISC-V and MIPS • RISC-V is an open source ISA – To be used by some companies for controllers (Nvidia and WD), for FPGA (Microsemi), for fitness bands… – For the time being, not targeting the data center – Might compete with ARM in the mid term – Completely eclipsed MIPS • MIPS – Considered dead 28/03/2019 35

Discrete GPUs: current status • GPU’s raw power follows the exponential trend on numbers of transistors and cores • New features appear unexpectedly, driven by market (e. g. tensor cores) – Tensor cores: programmable matrix-multiply-andaccumulate units – Fast half precision multiplication and reduction in full precision – Useful for accelerating deep learning training/inference 28/03/2019 https: //devblogs. nvidia. com/programming-tensor-cores-cuda-9/ 36

Nvidia and AMD • Volta addressing the server market, Turing the gaming market Feature Volta (V 100) Turing (2080 Ti) Process 12 nm CUDA cores yes Tensor cores yes RT cores NA yes FP performance FP 16: 28 TFLOPS FP 32: 14 TFLOPS FP 64: 7 TFLOPS Tensor: 112 TFLOPS Same, but FP 64: 1/32 of FP 32 Memory HBM 2 GDDR 6 Memory bandwidth 900 GB/sec 616 GB/sec Multi-GPU NVLink 2/SLI Applications AI, datacenter, workstation AI, workstation, gaming 28/03/2019 • Vega 20 – Directly aimed at the server world (Instinct MI 50 and MI 60) • Evolution of Vega 10 using a 7 nm process – – more space for HBM 2 memory, up to 32 GB 2 x memory bandwidth Massive FP 64 gains PCIe Gen 4 • Some improvements relevant for inference scenarios – Support for INT 8 and INT 4 data types – Some new instructions 37

GPUs - Programmability • NVIDIA CUDA: – C++ based (supports C++14), de-facto standard – New hardware features available with no delay in the API • Open. CL: – Can execute on CPUs, AMD GPUs and recently Intel FPGAs – Overpromised in the past, with scarce popularity • Compiler directives: Open. MP/Open. ACC – Latest GCC and LLVM include support for CUDA backend • AMD HIP: – Interfaces to both CUDA and AMD MIOpen, still supports only a subset of the CUDA features • GPU-enabled frameworks to hide complexity (Tensorflow) • Issue is performance portability and code duplication 28/03/2019 38

GPUs in LHC experiments software frameworks • Alice, O 2 – Tracking in TPC and ITS – Modern GPU can replace 40 CPU cores • CMS, CMSSW – Demonstrated advantage of heterogeneous reconstruction from RAW to Pixel Vertices at the CMS HLT – ~10 x both in speed-up and energy efficiency wrt full Xeon socket – Plans to run heterogeneous HLT during LHC Run 3 28/03/2019 • LHCb (online - standalone) Allen framework: HLT-1 reduces 5 TB/s input to 130 GB/s: – Track reconstruction, muon-id, two-tracks vertex/mass reconstruction – GPUs can be used to accelerate the entire HLT-1 from RAW data – Events too small, have to be batched: makes the integration in Gaudi difficult • ATLAS – Prototype for HLT track seed-finding, calorimeter topological clustering and antikt jet reconstruction – No plans to deploy this in the trigger for Run 3 39

FPGA • Players: Xilinx (US), Intel (US), Lattice Semiconductor (US), Microsemi (US), and Quick. Logic (US), TSMC (Taiwan), Microchip Technology (US), United Microelectronics (Taiwan), GLOBALFOUNDRIES (US), Achronix (US), and S 2 C Inc. (US) • Market valued at USD 5 Billion in 2016 and expected to be valued at 10 Billion in 2023 • Growing demand for advanced driverassistance systems (ADAS), developments in Io. T and reduction in time-to-market are the key driving factors 28/03/2019 20 nm 16 nm 14 nm Intel® Xilinx® Intel® Process Technology Intel® Xilinx® Top Performance Tier Virtex® Ultra. Scale® Virtex® Ultra. Scale+® Intel® Zynq® Ultra. Scale+® Stratix® 10 Mid Performance Tier Intel® Arria® 10 Kintex Ultra. Scale® Low Performance Tier Intel® Cyclone® 10 GX Xilinx® 40 Source: https: //www. intel. com/content/www/us/en/programmable/documentation/mtr 1422491996806. html#qom 1512594527835__fn_soc_variab_avail_xlx

FPGA programming • Used as an application acceleration device – Targeted at specific use cases • Neural inference engine • MATLAB • Lab. VIEW FPGA • Open. CL – Very high-level abstraction – Optimized for data parallelism • C / C++ / System C – High level synthesis (HLS) – Control with compiler switches and configurations • In HEP – High Level Triggers • https: //cds. cern. ch/record/2647951 – Deep Neural Networks • https: //arxiv. org/abs/1804. 06913 • https: //indico. cern. ch/event/703881/ – High Throughput Data Processing • https: //indico. cern. ch/event/669298/ • VHDL / Verilog – Low level programming 28/03/2019 41

MEMORY TECHNOLOGIES 28/03/2019 43

Static RAM (SRAM) • On die memory on the CPU used for L 1/L 2/L 3 cache – SRAM cell size not scaling with node • SRAM cache constitutes large fraction of area on modern CPUs • Power consumption is an issue • Applications driving larger caches • No direct replacement in sight for L 1/L 2 • Alternate L 3 cache technologies – e. DRAM - Used in IBM Power CPUs – STT-MRAM - proposed as possible replacement 28/03/2019 https: //www. sigarch. org/whats-the-future-of-technology-scaling/ 44

Dynamic RAM (DRAM) • Dominant standards continue to evolve – DDR 4 -> DDR 5 • 3200 MT/s -> 6400 MT/s • 16 Gb -> 32 Gb chips – GDDR 5 - > GDDR 5 X • 14 Gbps/pin -> 16 Gbps/pin • 8 Gb -> 16 Gb chips – HBM -> HBM 2 • 1 Gbps/pin -> 2. 4 Gbps/pin • 4 die stack -> 12 die stack • 2 Gb die -> 8 Gb die • Note memory latency remains mostly unchanged 28/03/2019 (Youngwoo Kim, KAIST’s Terabyte Labs) https: //www. 3 dincites. com/2019/02/designcon-2019 -shows-board-and-system-designersthe-benefits-of-advanced-ic-packaging/ 45

DRAM Outlook • Major vendors showing next generation chips (DDR 5/GDDR 6) • Multiple technologies being investigated for future DRAM • EUV lithography not needed for at least 3 more generations (Micron) • Contract DRAM pricing fell ~30% in Q 1 2019 • Pressure expected on DRAM prices thru 2019 due to additional production capacity coming online 28/03/2019 https: //www. techinsights. com/technology-intelligence/overview/technology-roadmaps/ 46

Emerging technologies • May eventually fill the gap – STT-MRAM between SRAM and DRAM (work in progress) – “Persistent Memory” in NVDIMM package for the DRAM/NAND gap • Low latency NAND (e. g. Z-NAND) • 3 D XPoint (aka “Optane”) – Technologies still in the lab • • • 28/03/2019 MRAM NRAM Fe. RAM PCRAM Re. RAM https: //www. snia. org/sites/default/files/PMSummit/2018/presentations/14_PM_Summit_18_Analysts_Session_Oros_Final_Post_UPD ATED_R 2. pdf 48

SUPPORTING TECHNOLOGIES 28/03/2019 49

Interconnect technology • Increasing requirements on bandwidth and latency driving the development – E. g. moving data between CPU and GPU is often a bottleneck – Several standards competing (PCIe Gen 4/5, CCIX, Gen-Z, Open. CAPI, CXL…) • Proprietary technologies – NVLink (GPU-to-GPU, GPU-to. POWER 9) – Ultra Path (Intel), CPU-to-CPU – Infinity Fabric (AMD), chiplet-tochiplet 28/03/2019 50

Packaging technology • Traditionally a silicon die is individually packaged, but more and more CPUs package together more (sometimes different) dies • Classified according to how dies are arranged and connected – 2 D packaging (e. g. AMD EPYC): multiple dies on a substrate – 2. 5 D packaging (e. g. Intel Kaby Lake-G, CPU+GPU): interposer between die and substrate for higher speed – Intel Foveros, a 2. 5 D with an interposer with active logic (Intel “Lake Field” hybrid CPU) – 3 D packaging (e. g. stacked DRAM in HBM), for lower power, higher bandwidth and smaller footprint • Can alleviate scaling issues with monolithic CPU dies but at a cost, both financial and in power and latency 28/03/2019 51

What next? • We do not really know what will be there in the HL-LHC era (2026 -2037) • Some “early indicators” of what might come next – Several nanoelectronics projects might help in • Increasing density of memory chips • Reducing size of transistors in IC – Nanocrystals, silicon nanophotonics, carbon nanotubes, single-atom thick graphene film, etc. – https: //www. understandingnano. com/nanotechnology-electronics. html 28/03/2019 52

Conclusions • Market trends – Server market is increasing, AMD share as well – EUV lithography driving 7 nm mass production • CPU, GPUs and accelerators – – AMD EPYC promising from a cost perspective Nvidia GPUs still dominant due to the better software support Recent developments for GPUs greatly favor inference workloads FPGA market dominated by telecom, industry and automotive but there is also some HEP usage • Memory technologies – SDRAM still the on-chip memory of choice, DRAM still for the main memory, no improvements in latency – NVDIMM – emerging memory packaging for memory between DRAM and NAND flash (see next talk) – Other non-volatile memory technologies in development 28/03/2019 53

Meta Conclusions • Some years ago: Concern that evolution may stop due to physics or technology • Now: Business, market, financial arguments are the real limit • Markets largely saturated • Tech watch is becoming essential for us and other Big Science communities • Comples and demanding but also interesting and rewarding 28/03/2019 54

References • Presentations: – HOW 2019 workshop: https: //indico. cern. ch/event/759388/sessions/295048/#20190319 – HEPi. X spring 2019 workshop: https: //indico. cern. ch/event/765497/sessions/303981/#20190328 • • Techwatch WG internal Web site: http: //w 3. hepix. org/techwatch/ Subgroup documents: – CPUs, GPUs and accelerators: https: //docs. google. com/document/d/1 d. Ucuu. Sub. LO 4 We. Fz. F 0 mls. A 8 m. Pg. HV-46 z 6 Rga 7 w. Ct 0 k. Fk/edit? usp=sharing – Memory: https: //docs. google. com/document/d/1 a 8 K_BA 8 ipy 5 l 0 Nvc. Njr. OLq. Ds. N_Rj. JXDn. X 4 LHRrfr. NE 0/edit? usp=sharing – Storage: https: //docs. google. com/document/d/1 IS 4_raw 7 PE 0 w. VTNWDJm. UGmne. V 1 zpg 9 -29 vz 7 XP 4 Ch. RA/edit – Networking: https: //twiki. cern. ch/twiki/bin/view/HEPIX/Techwatch. Network/Web. Home 28/03/2019 55

Backup Slide CCR Workshop June 2019 56

Network: Ethernet • 2019 – Support for links at 50, 200, 400 Gbps over single-mode fibre up to 10 km, to extend to 40 km later – Bi-directional optical PHY for point-topoint at 10, 25, 50 Gbps – 100 and 400 Gbps over DWDM up to 80 km • 100 Gbps becoming commodity, but too many variants; 400 Gbps is out • SC 18 demonstrated maturity of 100 Gbps servers 08 -May-2019 57

Forward Error Correction • Inflates payload by N bits to protects M bits – E. g. 300 / 5140 [RS(544, 514, 10)] or less for other standards • Little additional latency: O(100 ns) • Algorithms tuned to transmission parameters • Can use lower quality optical specs to reduce cost significantly • Requires less retransmits as long as all errors can be corrected → overall higher bandwidth • Can show ‘cliff’ in bandwidth if corrections fail due to too many transmission errors 08 -May-2019 58

Silicon Photonics • Almost all parts on same die – Cheaper to produce than traditional transceivers – Allows also for more integration testing – Manufacturing in existing CMOS production processes – Lower power consumption than conventional transceivers – Available since ~2 years from Cisco(Luxtera), Intel, Global. Foundries, IBM (research only? ), … • See also e. g. https: //community. mellanox. com/s/articl e/inside-the-silicon-photonics-transceiver 08 -May-2019 h

Areas of Network Evolution • Improving efficiency of data transfers – TCP BBR - version 2 is in the works with promising improvements – Exploring alternative protocols for transfers (UDP) • Caching – Data caches co-located with network hubs in a similar way as on commercial CDNs • Federations/Clouds – Overlay networks spanning multiple domains – Multi-clouds - expanding DC networking via L 3 VPNs • Technology – SDN/NFV approaches - currently looked at by HEPi. X NFV WG • Compute - Agile service delivery on Cloud Infrastructures (Open. Stack, Kubernetes) • Data Transfers - Network resource optimisation - dynamically optimising the network based on its load and state (more in Shawn/Ilija) – SD-WAN approaches - https: //www. mode. net/

Network: Other things to look out • What to expect from Mellanox/NVidia deal? – Nvidia paid $6. 9 b for Mellanox (~$1 b revenue) – 3 CPU/GPU(FPGA) interconnects now: • NVlink / Open. CAPI (Coherent Accelerator Processor Interface) AMD, IBM, Google, Micron, Mellanox (Nvidia as ‘contributor’) • CCIX (Cache Coherent Interconnect for Accelerators) AMD, ARM, IBM, Qualcomm, Xilinx, Huawei, Mellanox • CXL (Compute Express Link) Cisco, Dell EMC, Facebook, Google, HPE, Huawei, Intel, Microsoft • Remote DMA (RDMA) with all its flavours – Ro. CE RDMA over Converged Ethernet, i. WARP, . . . 9