HCal frontend ASIC Status LAL Orsay J Fleury

H-Cal front-end ASIC Status LAL Orsay J. Fleury, C. de la Taille, G. Martin, L. Raux 1

Contents 1. Si. PM Readout Prototype Ø DAC for gain Adjustement Ø 1 st option : Preamp+CRRC 2 shaper Ø 2 nd option : Unipolar version: RC 6 shaper: Ø Backup option : FLC_PHY 3 2. Conclusion and perspectives Ø Production schedule Ø Production cost 2

Si. PM Readout Prototype Chip n 18 -Channel Readout Chip Prototype Ø Ø Ø Technology AMS 0. 8 m CMOS – Submitted in June 2004 DAC for Si PM Gain adjustment – Received in September 2004 Preamplifier + Shaper CRRC 2 Unipolar solution RC 6 shaper Track & Hold and multiplexed output (OPERA and FLC_PHY 3) +HV 100 kΩ 100 n. F Si. PM 8 -bit DAC 50Ω 100 n. F input ASIC 3

DAC Schematic n Adjustement gain DAC 8 -bit DAC excursion 1 -5 V Ø Based on ratioed mirror Ø OTA to avoid early effect (virtual ground) Ø 4

Channel CRRC 2 architecture for Si. PM 100 MΩ 8 -bit 40 kΩ 0. 1 p. F 0. 2 p. F DAC 1 -5 V 1. 2 p. F 0. 4 p. F 0. 6 p. F 0. 8 p. F in 50Ω 2. 4 p. F ASIC 0. 3 p. F 12 kΩ 4 kΩ 10 p. F 5 kΩ 8 p. F 4 p. F 2 p. F 1 p. F 24 p. F 12 p. F 6 p. F 100 n. F Test_pulse Variable Gain Charge Preamplifier 3 p. F Variable Shaper CR -RC² 5

Full simulation CRRC 2 n Calibration mode Single photoelectron response Ø Cf=0. 2 p. F ; τ =12 ns Ø 1 spe = 8. 9 m. V ; tp=40 ns Ø Noise : 720 µV rms Ø n Physics mode MIP (=16 pe) response Ø Cf=0. 4 p. F ; Rc=5 k ; τ =120 ns Ø Gain = 12 m. V/MIP ; tp=186 ns Ø Noise = 570 µV rms Ø Cf=0. 4 p. F; Rc=0 ; τ =180 ns Ø Gain =14 m. V/MIP ; tp=150 ns Ø Noise = 220 µV Ø Ø Swing voltage: ~2. 5 V 6

RC 6 architecture n Unipolar architecture RC 6 Shaper n Composed with 3 successive RC 2 shaper τ=38 ns n OTA used for biasing 3. 5 kΩ 5 p. F + - 11 p. F 7 kΩ Vout Vin 2. 8 kΩ Switch for calibration mode - OTA Vref + 5. 5 p. F Gm=1 u. A/V OFF calibration mode/ ON physics mode 7

Full simulation RC 6 1 MIP response * 125 n Calibration mode Single photoelectron response (1 pe=160 f. C) Ø Gain 9 m. V/pe tp=30 ns Ø Noise : 1. 4 m. V rms Ø 125 MIP response n Physics mode Ø Ø Ø MIP (=16 pe) response Gain 17 m. V/MIP tp=200 ns 1 pe response Noise = 800 µV rms Dynamic Range [1 -125]MIP Linearity <1% Swing voltage: ~2. 5 V 1 MIP=16 pe response 8

Backup: FLC_PHY 3 n No gain adjustement gain DAC n No Variable shaping No Calibration mode n Measurement in progress n 1000 chips available 5 kΩ 10 p. F 50Ω 200 p. F FLC_PHY 3 9

Schedule Ø Prototype Submission in June 2004 Ø Prototype Delivery in September 2004 Ø Test and validation with Si. PM in October 2004 Ø Production (1000 chips) of the validated version could start in November 2004 Ø Production Delivery expected in January 2005 Ø Systematic chips test in February 2005 Ø Chips available for the collaboration by March-April 2005 10

Production cost estimation n Silicon : 1000 dies (area: ~10 mm² ) 2 wafers needed: 39 k Euros – Mask : 35 k Euros – Silicon : 4 k Euros n Package : PQFP-100 : 4 k Euros n Total : 43 k Euros n Maybe possibility to share the production with other lab to decrease the production cost 11