Hardware Description Languages Digital Design and Computer Architecture

Chapter 4 : : Topics • • Introduction Combinational Logic Structural Modeling Sequential Logic

Introduction • Hardware description language (HDL): allows designer to specify logic function only. Then

HDL to Gates • Simulation – Input values are applied to the circuit –

Verilog Example Verilog: module example(input a, b, c, output y); assign y = ~a

Verilog Simulation Verilog: module example(input a, b, c, output y); assign y = ~a

Verilog Synthesis Verilog: module example(input a, b, c, output y); assign y = ~a

Verilog Syntax • Case sensitive – Example: reset and Reset are not the same

Boolean Equations in Verilog • Use logical operators in assignment statements module circuit (

Structural Modeling - Hierarchy module and 3(input a, b, c, output y); assign y

Bitwise Operators module gates(input [3: 0] a, b, output [3: 0] y 1, y

Reduction Operators module and 8(input [7: 0] a, output y); assign y = &a;

Boolean Equation Example • Air conditioner control logic module aircon ( output heater_on, cooler_on,

Conditional Assignment module mux 2(input [3: 0] d 0, d 1, input s, output

Internal Variables module fulladder(input a, b, cin, output s, cout); wire p, g; //

Precedence Defines the order of operations Highest ~ NOT *, /, % mult, div,

Verilog Logical Operators a & b a | b ~(a & b) ~(a |

Numbers Format: N'Bvalue N = number of bits, B = base N'B is optional

Scaling in Verilog • Shift-left (<<) and shift-right (>>) operations – result is same

$Bit Manipulations: Example 1 assign y = {a[2: 1], {3{b[0]}}, a[0], 6’b 100_010}; //$

Bit Manipulations: Example 2 Verilog: module mux 2_8(input [7: 0] d 0, d 1,

Z: Floating Output Verilog: module tristate(input [3: 0] a, input en, output [3: 0]

Other Behavioral Statements • Statements that must be inside always statements: – if /

Combinational Logic using always // combinational logic using an always statement module gates(input [3:

Combinational Components • We can build complex combination components from gates – Decoders, encoders

Decoders • A decoder derives control signals from a binary coded signal – One

Decoder Example Copyright © 2007 Elsevier Color Codeword (c 2, c 1, c 0)

Decoder Example module ink_jet_decoder ( output black, cyan, magenta, yellow, light_cyan, light_magenta, input color

Encoders • An encoder encodes which of several inputs is 1 – Assuming (for

Encoder Example • Burglar alarm: encode which zone is active Copyright © 2007 Elsevier

Encoder Example module alarm_eqn ( output [2: 0] intruder_zone, output valid, input [1: 8]

Priority Encoders • If more than one input can be 1 – Encode input

Priority Encoder Example module alarm_priority_1 ( output [2: 0] intruder_zone, output valid, input [1:

BCD Code • Binary coded decimal – 4 -bit code for decimal digits 0:

Combinational Logic using case • In order for a case statement to imply combinational

Seven-Segment Decoder • Decodes BCD to drive a 7 -segment LED or LCD display

Seven-Segment Decoder module seven_seg_decoder ( output [7: 1] seg, input [3: 0] bcd, input

Blocking vs. Nonblocking Assignments • <= is a “nonblocking assignment” – Occurs simultaneously with

Adders in Verilog • Use arithmetic “+” operator wire [7: 0] a, b, s;

Increment/Decrement in Verilog • Just add or subtract 1 wire [15: 0] x, s;

Equality Comparison • XNOR gate: equality of two bits – Apply bitwise to two

Inequality Comparison • Magnitude comparator for x > y Copyright © 2007 Elsevier 4

Comparison Example in Verilog • Thermostat with target termperature – Heater or cooler on

Sequential Logic • Verilog uses certain idioms to describe latches, flip-flops and FSMs •

Rules for Signal Assignment • Use always @(posedge clk) and nonblocking assignments (<=) to

D Flip-Flop module flop(input clk, input [3: 0] d, output reg [3: 0] q);

Resettable D Flip-Flop module flopr(input clk, input reset, input [3: 0] d, output reg

D Flip-Flop with Enable module flopren(input clk, input reset, input en, input [3: 0]

Latch module latch(input clk, input [3: 0] d, output reg [3: 0] q); always

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Chapter 4 : : Topics • • Introduction Combinational Logic Structural Modeling Sequential Logic More Combinational Logic Finite State Machines Parameterized Modules Testbenches Copyright © 2007 Elsevier 4 -<2>

Introduction • Hardware description language (HDL): allows designer to specify logic function only. Then a computer-aided design (CAD) tool produces or synthesizes the optimized gates. • Most commercial designs built using HDLs • Two leading HDLs: – Verilog • developed in 1984 by Gateway Design Automation • became an IEEE standard (1364) in 1995 – VHDL • Developed in 1981 by the Department of Defense • Became an IEEE standard (1076) in 1987 Copyright © 2007 Elsevier 4 -<3>

HDL to Gates • Simulation – Input values are applied to the circuit – Outputs checked for correctness – Millions of dollars saved by debugging in simulation instead of hardware • Synthesis – Transforms HDL code into a netlist describing the hardware (i. e. , a list of gates and the wires connecting them) IMPORTANT: When describing circuits using an HDL, it’s critical to think of the hardware the code should produce. Copyright © 2007 Elsevier 4 -<4>

Verilog Syntax • Case sensitive – Example: reset and Reset are not the same signal. • No names that start with numbers – Example: 2 mux is an invalid name. • Whitespace ignored • Comments: – // single line comment – /* multiline comment */ Copyright © 2007 Elsevier 4 -<9>

Boolean Equations in Verilog • Use logical operators in assignment statements module circuit ( output f, input x, y, z ); assign f = (x | (y & ~z)) & ~(y & z); endmodule • What is the synthesized logic? Copyright © 2007 Elsevier 4 -<10>

Structural Modeling - Hierarchy module and 3(input a, b, c, output y); assign y = a & b & c; endmodule También se puede escribir: and 3 andgate(. y(n 1), . a(a), . b(b), . c(c)) module inv(input a, output y); assign y = ~a; endmodule nand 3(input a, b, c output y); wire n 1; // internal signal and 3 andgate(a, b, c, n 1); // instance of and 3 inverter(n 1, y); // instance of inverter endmodule Copyright © 2007 Elsevier 4 -<11>

Bitwise Operators module gates(input [3: 0] a, b, output [3: 0] y 1, y 2, y 3, y 4, y 5); /* Five different two-input logic gates acting on 4 bit busses */ assign y 1 = a & b; // AND assign y 2 = a | b; // OR assign y 3 = a ^ b; // XOR assign y 4 = ~(a & b); // NAND assign y 5 = ~(a | b); // NOR endmodule // /*…*/ Copyright © 2007 Elsevier single line comment multiline comment 4 -<12>

Reduction Operators module and 8(input [7: 0] a, output y); assign y = &a; // &a is much easier to write than // assign y = a[7] & a[6] & a[5] & a[4] & // a[3] & a[2] & a[1] & a[0]; endmodule Copyright © 2007 Elsevier 4 -<13>

Boolean Equation Example • Air conditioner control logic module aircon ( output heater_on, cooler_on, fan_on, input temp_low, temp_high, auto_temp, input manual_heat, manual_cool, manual_fan ); assign heater_on = (temp_low & auto_temp) | manual_heat; assign cooler_on = (temp_high & auto_temp) | manual_cool; assign fan_on = heater_on | cooler_on | manual_fan; endmodule • What is the synthesized Logic? Copyright © 2007 Elsevier 4 -<14>

Conditional Assignment module mux 2(input [3: 0] d 0, d 1, input s, output [3: 0] y); assign y = s ? d 1 : d 0; endmodule ? : Copyright © 2007 Elsevier is also called a ternary operator because it operates on 3 inputs: s, d 1, and d 0. 4 -<16>

Internal Variables module fulladder(input a, b, cin, output s, cout); wire p, g; // internal nodes assign p = a ^ b; assign g = a & b; assign s = p ^ cin; assign cout = g | (p & cin); endmodule Copyright © 2007 Elsevier 4 -<17>

Precedence Defines the order of operations Highest ~ NOT *, /, % mult, div, mod +, - add, sub <<, >> shift <<<, >>> arithmetic shift <, <=, >, >= comparison Lowest Copyright © 2007 Elsevier ==, != equal, not equal &, ~& AND, NAND ^, ~^ XOR, XNOR |, ~| OR, XOR ? : ternary operator 4 -<18>

Verilog Logical Operators a & b a | b ~(a & b) ~(a | b) • Precedence – not has highest – then &, then ^ and ~^, then | – use parentheses to make order of evaluation clear • Verilog bit values – 1'b 0 and 1'b 1 a ^ b a ~^ b ~a Copyright © 2007 Elsevier 4 -<19>

Numbers Format: N'Bvalue N = number of bits, B = base N'B is optional but recommended (default is decimal) Number # Bits Base Decimal Equivalent Stored 3’b 101 3 binary 5 101 ‘b 11 unsized binary 3 00… 0011 8’b 11 8 binary 3 00000011 8’b 1010_1011 8 binary 171 10101011 3’d 6 3 decimal 6 110 6’o 42 6 octal 34 100010 8’h. AB 8 hexadecimal 171 10101011 42 Unsized decimal 42 00… 0101010 Copyright © 2007 Elsevier 4 -<20>

Scaling in Verilog • Shift-left (<<) and shift-right (>>) operations – result is same size as operand s = 000100112 = 1910 assign y = s << 2; assign y = s >> 2; y = 010011002 = 7610 y = 000001002 = 410 Copyright © 2007 Elsevier 4 -<21>

$Bit Manipulations: Example 1 assign y = {a[2: 1], {3{b[0]}}, a[0], 6’b 100_010}; //$

Bit Manipulations: Example 1 assign y = {a[2: 1], {3{b[0]}}, a[0], 6’b 100_010}; // if y is a 12 -bit signal, the above statement produces: y = a[2] a[1] b[0] a[0] 1 0 0 0 1 0 // underscores (_) are used formatting only to make it easier to read. Verilog ignores them. Copyright © 2007 Elsevier 4 -<22>

Bit Manipulations: Example 2 Verilog: module mux 2_8(input [7: 0] d 0, d 1, input s, output [7: 0] y); mux 2 lsbmux(. d 0(d 0[3: 0]), . d 1(d 1[3: 0]), . s(s), . y(y[3: 0])); mux 2 msbmux(. d 0(d 0[7: 4]), . d 1(d 1[7: 4]), . s(s), . y(y[7: 4])); endmodule Synthesis: Copyright © 2007 Elsevier 4 -<23>

Other Behavioral Statements • Statements that must be inside always statements: – if / else – case, casez • Reminder: Variables assigned in an always statement must be declared as reg (even if they’re not actually registered!) Copyright © 2007 Elsevier 4 -<27>

Combinational Logic using always // combinational logic using an always statement module gates(input [3: 0] a, b, output reg [3: 0] y 1, y 2, y 3, y 4, y 5); always @(*) // need begin/end because there is begin // more than one statement in always y 1 = a & b; // AND y 2 = a | b; // OR y 3 = a ^ b; // XOR y 4 = ~(a & b); // NAND y 5 = ~(a | b); // NOR endmodule This hardware could be described with assign statements using fewer lines of code, so it’s better to use assign statements in this case. Copyright © 2007 Elsevier 4 -<28>

Combinational Components • We can build complex combination components from gates – Decoders, encoders – Multiplexers – … • Use them as subcomponents of larger systems – Abstraction and reuse Copyright © 2007 Elsevier 4 -<29>

Decoders • A decoder derives control signals from a binary coded signal – One per code word – Control signal is 1 when input has the corresponding code word; 0 otherwise • For an n-bit code input – Decoder has 2 n outputs • Example: (a 3, a 2, a 1) – Output for (1, 0, 1, 1): Copyright © 2007 Elsevier 4 -<30>

Decoder Example module ink_jet_decoder ( output black, cyan, magenta, yellow, light_cyan, light_magenta, input color 2, color 1, color 0 ); assign assign black cyan magenta yellow light_cyan light_magenta = ~color 2 & ~color 1 & color 0; = ~color 2 & color 1 & ~color 0; = ~color 2 & color 1 & color 0; = color 2 & ~color 1 & ~color 0; = color 2 & ~color 1 & color 0; = color 2 & color 1 & ~color 0; endmodule Copyright © 2007 Elsevier 4 -<32>

Encoders • An encoder encodes which of several inputs is 1 – Assuming (for now) at most one input is 1 at a time • What if no input is 1? – Separate output to indicate this condition Copyright © 2007 Elsevier 4 -<33>

Encoder Example • Burglar alarm: encode which zone is active Copyright © 2007 Elsevier Zone 1 Zone 2 Zone 3 Codeword 0, 0, 0, 1, 0 Zone 4 Zone 5 Zone 6 Zone 7 Zone 8 0, 1, 1 1, 0, 0 1, 0, 1 1, 1, 0 1, 1, 1 4 -<34>

Priority Encoders • If more than one input can be 1 – Encode input that is 1 with highest priority zone intruder_zone valid (1) (2) (3) (4) (5) (6) (7) (8) (2) (1) (0) 1 – – – – 0 0 0 1 – – – 0 0 1 1 0 0 1 – – – 0 1 0 0 0 1 – – 0 1 1 1 0 0 1 – – – 1 0 0 0 0 0 1 – – 1 0 1 1 0 0 0 1 – 1 1 0 0 0 0 1 1 1 0 0 0 0 – – – 0 Copyright © 2007 Elsevier 4 -<36>

Priority Encoder Example module alarm_priority_1 ( output [2: 0] intruder_zone, output valid, input [1: 8] zone ); assign intruder_zone = zone[1] zone[2] zone[3] zone[4] zone[5] zone[6] zone[7] zone[8] 3'b 000; ? ? ? ? 3'b 000 3'b 001 3'b 010 3'b 011 3'b 100 3'b 101 3'b 110 3'b 111 : : : : assign valid = zone[1] | zone[2] | zone[3] | zone[4] | zone[5] | zone[6] | zone[7] | zone[8]; endmodule Copyright © 2007 Elsevier 4 -<37>

Combinational Logic using case • In order for a case statement to imply combinational logic, all possible input combinations must be described by the HDL. • Remember to use a default statement when necessary. Copyright © 2007 Elsevier 4 -<39>

Seven-Segment Decoder module seven_seg_decoder ( output [7: 1] seg, input [3: 0] bcd, input blank ); reg [7: 1] seg_tmp; always @* case (bcd) 4'b 0000: 4'b 0001: 4'b 0010: 4'b 0011: 4'b 0100: 4'b 0101: 4'b 0110: 4'b 0111: 4'b 1000: 4'b 1001: default: endcase seg_tmp seg_tmp seg_tmp = = = 7'b 0111111; 7'b 0000110; 7'b 1011011; 7'b 1001111; 7'b 1100110; 7'b 1101101; 7'b 1111101; 7'b 0000111; 7'b 1111111; 7'b 1101111; 7'b 1000000; // // // 0 1 2 3 4 5 6 7 8 9 "-" for invalid code assign seg = blank ? 7'b 0000000 : seg_tmp; endmodule Copyright © 2007 Elsevier 4 -<41>

Blocking vs. Nonblocking Assignments • <= is a “nonblocking assignment” – Occurs simultaneously with others • = is a “blocking assignment” – Occurs in the order it appears in the file // Good synchronizer using // nonblocking assignments module syncgood(input clk, input d, output reg q); reg n 1; always @(posedge clk) begin n 1 <= d; // nonblocking q <= n 1; // nonblocking endmodule Copyright © 2007 Elsevier // Bad synchronizer using // blocking assignments module syncbad(input clk, input d, output reg q); reg n 1; always @(posedge clk) begin n 1 = d; // blocking q = n 1; // blocking endmodule 4 -<43>

Adders in Verilog • Use arithmetic “+” operator wire [7: 0] a, b, s; . . . assign s = a + b; wire [8: 0] tmp_result; wire c; . . . assign tmp_result = {1'b 0, a} + {1'b 0, b}; assign c = tmp_result[8]; assign s = tmp_result[7: 0]; assign {c, s} = {1'b 0, a} + {1'b 0, b}; assign {c, s} = a + b; Copyright © 2007 Elsevier 4 -<44>

Increment/Decrement in Verilog • Just add or subtract 1 wire [15: 0] x, s; . . . assign s = x + 1; // increment x assign s = x - 1; // decrement x • Note: 1 (integer), not 1'b 1 (bit) – Automatically resized Copyright © 2007 Elsevier 4 -<45>

Equality Comparison • XNOR gate: equality of two bits – Apply bitwise to two unsigned numbers • In Verilog, x == y gives a bit result – 1'b 0 for false, 1'b 1 for true assign eq = x == y; Copyright © 2007 Elsevier 4 -<46>

Comparison Example in Verilog • Thermostat with target termperature – Heater or cooler on when actual temperature is more than 5° from target module thermostat ( output heater_on, cooler_on, input [7: 0] target, actual ); assign heater_on = actual < target - 5; assign cooler_on = actual > target + 5; endmodule • How is it synthesized? Copyright © 2007 Elsevier 4 -<48>

Rules for Signal Assignment • Use always @(posedge clk) and nonblocking assignments (<=) to model synchronous sequential logic always @ (posedge clk) q <= d; // nonblocking • Use continuous assignments (assign …)to model simple combinational logic. assign y = a & b; • Use always @ (*) and blocking assignments (=) to model more complicated combinational logic where the always statement is helpful. • Do not make assignments to the same signal in more than one always statement or continuous assignment statement. Copyright © 2007 Elsevier 4 -<50>

D Flip-Flop module flop(input clk, input [3: 0] d, output reg [3: 0] q); always @ (posedge clk) q <= d; // pronounced “q gets d” endmodule Any signal assigned in an always statement must be declared reg. In this case q is declared as reg Beware: A variable declared reg is not necessarily a registered output. We will show examples of this later. Copyright © 2007 Elsevier 4 -<51>

Resettable D Flip-Flop module flopr(input clk, input reset, input [3: 0] d, output reg [3: 0] q); // synchronous reset always @ (posedge clk) if (reset) q <= 4'b 0; else q <= d; endmodule Copyright © 2007 Elsevier 4 -<52>

Resettable D Flip-Flop module flopr(input clk, input reset, input [3: 0] d, output reg [3: 0] q); // asynchronous reset always @ (posedge clk, posedge reset) if (reset) q <= 4'b 0; else q <= d; endmodule Copyright © 2007 Elsevier 4 -<53>

D Flip-Flop with Enable module flopren(input clk, input reset, input en, input [3: 0] d, output reg [3: 0] q); // asynchronous reset and enable always @ (posedge clk, posedge reset) if (reset) q <= 4'b 0; else if (en) q <= d; endmodule Copyright © 2007 Elsevier 4 -<54>

Latch module latch(input clk, input [3: 0] d, output reg [3: 0] q); always @ (clk, d) if (clk) q <= d; endmodule Warning: We won’t use latches in this course, but you might write code that inadvertently implies a latch. So if your synthesized hardware has latches in it, this indicates an error. Copyright © 2007 Elsevier 4 -<55>