Hardware Acceleration of the Lifting Based DWT Vidhu

Hardware Acceleration of the Lifting Based DWT Vidhu Niti Singh Pritam Kulkarni

Background: The Lifting Scheme : Low Frequency Components Scaling Coefficients : High Frequency Components Wavelet Coefficients

Advantages Does not rely on Fourier Transform, hence can be made even more efficient. l Integer to Integer Transformation ¡ Maps integers to integers thus eliminating the use of floating point operations. ¡ This process is reversible and lossless. ¡ Good for Hardware implementation. l Large amount of parallelism available. l All computations done in place i. e. no extra registers needed to store the input. Registers are needed to store the filter/lifting coefficients though. l

Motivation l l l - Parallel operations in predicting one - Parallel operations in updating from one - Reusing data in predicting one - Reusing data in updating from one - Parallel execution of 1 -D predict and update phases - Reusing data in 1 -D predict and update phases

Parallelizing Predict Stage(1) All and filter coefficients known before hand. The entire operation Can be done in parallel Lambdas used for consecutive stages are stored in buffer to reduce number of memory accesses.

Parallelizing Predict Stage(2) The filter coefficients can be stored in a RAM/Registers in such a manner that they can be accessed in parallel.

Predict Module

Accelerating the update stage In the update stage we know all the lambdas and lifting coefficients Hence there is no data dependency within one cycle and we can do the entire cycle in parallel.

Update Module

Pipelining the predict and update stages A FIFO buffer is needed to accommodate for the different rate of production of gammas.

Work Done l Written the code ( MATLAB and C) for the predict and update modules for both – the forward and the inverse wavelet transform based on the lifting scheme. l Designed the Hardware shown above to help in the parallel implementation of the DWT. l Completed coding of the modules in Verilog HDL. Synthesized the same using Synopsis Design Compiler.

Results l Predict stage in a sequential machine needs l 16 memory accesses l 4 multiplication l 4 addition/subtraction ¡ The new scheme needs l 1 memory access l 1 clock for all the multiplications l 1 clock cycle for all additions/subtractions. l Exactly the same results for the update stage. l Apart from parallelism within the stages. This scheme allows pipelining of the two stages.