Graph Coloring Vertex Coloring problem in VLSI routing

Graph Coloring

Vertex Coloring problem in VLSI routing Share a track Standard cells channels Minimize channel width- assign horizontal Metal wires to tracks. . (min # of tracks = min channel width Share a track

Vertex Coloring problem in VLSI routing Standard cells 1 channels 2 3 4 Minimize channel width- assign horizontal Metal wires to tracks. . (min # of tracks = min channel width 5

Vertex=wire edge=overlapped wires color = track R 1 B R 2 4 5 3 G CHORDAL GRAPH B

Vertex Coloring problem in register allocation. Share a register channels TIME increasing Minimize # of registers: assign variable (lifetimes) to registers (min # of registers ) Share a register

Clique paritioning: edges are connected if there is no conflict (no overlapping wires, no overlapping lifetimes) R 1 B R 2 4 5 B 3 G COMPLEMENT OF CHORDAL GRAPH IS COMPARABILITY GRAPH

Clique paritioning: example R 4 1 R B 2 5 B 3 G

Garey & Johnson Text • Instance: graph G=(V, E), positive integer K<=|V|. • Question: is G K-colorable ? • Solvable in polynomial time for K=2, NPcomplete for K>=3. • General problem solvable in polynomial time for comparability graphs, chordal graphs, and others.

Also same for clique partitioning • Graph G=(V, E), K<=|V| • Question : can vertices of G be partitioned into k<=K disjoint sets V 1, V 2, …Vk such that for 1<=i<=k the subgraph induced by Vi is a complete graph?

In our application, our graphs are always chordal ! (in channel routing problem) a b c d a b d c?

Register allocation in loops coloring of a circular arc graph which is NP-complete a b c? d c? LOOP- variable c is defined in loop iteration i and used in the next loop iteration i+1 LOOP Time increasing

Channel routing is still a hard problem due to the vertical constraints Which we cannot accommodate in our graph theory formulation (which Only looks at horizontal constraints i. e. horizontal intervals) top down view