Graduate Institute of Electronics Engineering NTU Final project

Graduate Institute of Electronics Engineering, NTU Final project Speaker: Aeag (柯鴻洋) Advisor: Prof. Andy Wu 2003/05/29 ACCESS IC LAB

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Goal v Use fig. 8. 30 as an example to design your 1 -bit Edgetriggered DFF. Cascade four DFF’s to form a 4 -bit Data register. v Cascade four 1 -bit Full-adder(from Hw 3) to form a 4 -bit Ripple adder. v Use the 4 -bit Ripple Adder and 4 -bit Register to design an accumulator that can calculate The serial input are 1, 2, 3, 4, 5 one data at a clock. 2003/05/31 2

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Block diagram Input 4 -bit full-adder D-FF sum clk reset 2003/05/31 3

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Ex 1 for D-FF circuit Ref [1] 2003/05/31 4

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Ex 1 for D-FF circuit cont. Ref [1] 2003/05/31 5

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Ex 2 for D-FF circuit Ref [1] 2003/05/31 6

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Waveform for D-FF Ref [1] 2003/05/31 7

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Ex for 1 -bit Accumulator Ref [2] 2003/05/31 8

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Expected Waveform Ref [2] 2003/05/31 9

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Spice simulation 2003/05/31 Ref [2] 10

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Hand in v Using spice simulation to verify the function of 4 bit Ripple adder and 4 -bit data register respectively. v A plot of the layout for 4 -bit Ripple adder and 4 bit data register respectively. v Try to estimate the fasting clock rate. Use SPICE to simulate the speed of your circuit. 2003/05/31 11

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Hand in cont. v What would be the critical path of the accumulator design? Please discuss. v According requirement (3) to combine the circuit of (1) and (2) to form an accumulator, you need to hand in the accumulator layout. And the accumulator or the design flow from (layout=>DRC=>LVS) must be verified correctly. (DRC and LVS’s report should be no errors, and result should been contained in your final report) 2003/05/31 12

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Reference v [1] “CMOS Integrated Circuits: Analysis and Design, ” 3 rd Ed. , by Sung -Mo Kang and Yusuf Leblebici, Mc. Graw-Hill, 2003. v [2] http: //www-unix. ecs. umass. edu/~alaffely/ECE 658/2 Lab/l 2. html 2003/05/31 13

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Good luck! Thank you! 2003/05/31 14