Graduate Institute of Electronics Engineering NTU 102 1

Graduate Institute of Electronics Engineering, NTU 102 -1 Under-Graduate Project: RTL Coding Style Speaker: 黃乃珊 Adviser: Prof. An-Yeu Wu Date: 2013/12/12 ACCESS IC LAB

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Outline v Principles of RTL Coding Styles v v Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis v Debugging Tool: n. Lint P 2

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Pre-RTL Preparation Checklist v Communicate design issues with your teammates v Naming conventions, directory trees and other design organizations v Have a specification for your design v Everyone should have a specification BEFORE they start coding v Design partition v Follow the specification’s recommendations for partition v Break the design into major functional blocks P 3

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU RTL Coding Style Start Cmpt End v Create a block level drawing of your design before you begin coding. v Draw a block diagram of the functions and sub -functions of your design. v Hierarchy design v Always think of the poor guy who has to read your RTL code. yaya 66 Multiply_0 v Easy to understand. v Meaningful names. v Comments and headers. haha 55 Sum_2 P 4

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Outline v Principles of RTL Coding Styles v v Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis v Debugging Tool: n. Lint P 5

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU File Headers v Include informational header at the top of every source file, including scripts. v Filename v Author information, e. g. name, email… v Description of function and list of key features of the module v Available parameters v Reset scheme and clock domain v Date the file was created and modified v Critical timing and asynchronous interface P 6

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU File Header Example: DCT. v P 7

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Identifiers Naming Rule v Begin with an alpha character (a-z, A-Z) or an underscore (_) and can contain alphanumeric, dollar signs ($) and underscore. v Examples of illegal identifiers: Ø 34 net Ø a*b_net Ø n@238 v Up to 1023 characters long v Case sensitive v e. g. sel and SEL are different identifiers P 8

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU General Naming Conventions(1/3) v Lowercase letters for all signals, variables, and port names. v reg is used in procedural block v Uppercase letters for constants and user-defined types. v e. g. `define MEM_WIDTH 16 v Verilog is case sensitive v Meaningful names v Use ram_addr for RAM address bus instead of ra P 9

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU General Naming Conventions(2/3) v Use clk for the clock signal v If more than one clock, use clk as the prefix for all clock signals (clk 1, clk 2, clk_interface) v For active low signals, use *_n v If the reset signal is active low, use rst_n v Similarly, for active high signals, use *_p v For input of a register, use *_w v For output of a register, use *_r v For input signals, use *_i v For output signals, use *_o P 10

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Example Top Reg 1 data_i reg 1_w reg 1_r Com. Logic com 1_i Reg 2 com 1_o reg 2_w reg 2_r data_o assign reg 1_w = data_i; assign reg 2_w = com 1_o; assign com 1_i = reg 1_r; always @ (posedge clk_p) begin reg 1_r <= reg 1_w; reg 2_r <= reg 2_w; end always @(*) begin com 1_o = com 1_i + 4’d 5; end For connection Logic P 11

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU General Naming Conventions(3/3) v Use [x: 0] (instead of [0: x]) when describing multi-bit buses v A somewhat arbitrary suggested “standard” v Use parameter to improve readability v module car (out, in 1, in 2); ………… parameter S 0_STOP = 2’d 0, S 1_RUN = 2’d 1; ………… case (state) S 0_STOP: …. . v Don’t use HDL reserved words v e. g. xor, nand , module P 12

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Use comments v Use comments appropriately to explain v Brief, concise, explanatory v Avoid “comment clutter”– obvious functionality does not need to be commented v Single-line comments begin with // v Multiple-line comments start with /* and end with */ v Use indentation to improve the readability of continued code lines and nested loops v e. g. P 13

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Module Instantiation v Always use explicit mapping for ports, use named mapping rather than positional mapping module_a ( clk, s 1_i, s 1_o, s 2_i, s 2_o ); P 14

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Use loops and arrays v Using loop to increase readability v Loop is usually used as memory initialization for example: P 15

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Outline v Principles of RTL Coding Styles v v Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis v Debugging Tool: n. Lint P 16

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Finite State Machines v FSM have widespread application in digital systems. v Most frequently used in controller v Mealy Machine: The next state and the outputs depend on the present state and the inputs. v Moore Machine: The next state depends on the present state and the inputs, but the output depends on only the present state. output = f (In, CS) output = f (CS) P 17

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Modeling FSM in Verilog v Sequential Circuits v Memory elements of States (S) v Combinational Circuits v Next-state Logic (NL) v Output Logic (OL) v Three coding styles v (1) Separate S, OL and NL v (2) Combines NL+ OL, separate S Not recommended!! v (3) Combine S + NL, separate OL �� Mix the comb. and seq. circuits P 18

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Style (1) Separate S, NL, OL P 19

ACCESS IC LAB Style (2) Graduate Institute of Electronics Engineering, NTU Combine NL+OL; Separate S P 20

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Outline v Principles of RTL Coding Styles v v Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis v Debugging Tool: n. Lint P 22

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Reset Signal v Use the reset signal to initialize registered signals dct_r <= 1’b 0; dct_r <= dct_w; P 23

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Avoid Latches (1/2) v Avoid using any latches in your design v Use a design checking tool (n. Lint) to check for latches in your design v Poor Coding Styles v Latches inferred because of missing assignments and missing condition v Latch inferred because of missing else condition P 24

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Avoid Latches (2/2) v Avoid inferred latches v Fully assign outputs for all input conditions P 25

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Avoid Combinational Feedback P 26

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Sensitivity List (1/3) v For combinational blocks, the sensitivity list must include every signal that is read by the process. v Signals that appear on the right side of an assign statement v Signals that appear in a conditional expression v For simplicity, Verilog 2001 supports always @ (*) P 27

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Sensitivity List (2/3) v Include a complete sensitivity list in each of always blocks v If not, the behavior of the pre-synthesis design may differ from that of the post-synthesis netlist. P 28

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Sensitivity List (3/3) v For sequential blocks v The sensitive list must include the clock signal. v If an asynchronous reset signal is used, include reset in the sensitivity list. v Use only necessary signals in the sensitivity lists v Unnecessary signals in the sensitivity list slow down simulation P 29

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Combinational vs. Sequential Blocks v Combinational logic A v Use blocking (=) assignments v Execute in sequential order B sum_1 + + C v Sequential logic sum_2 clk v Use nonblocking (<=) assignments m 1_w v Execute concurrently v Do not make assignments to the same variable from more than one always block. always@(*) begin sum_1 = A + B; sum_2 = sum_1 + C; end m 1_r always@(posedge clk) begin m 1_r <= m 1_w; m 2_r <= m 2_w; end clk m 2_w m 2_r Multiple Assignment P 30

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU case Statement v Fully specified verilog case statements result in a singlelevel multiplexer v Partially specified Verilog case statements result in latches case (sel) 2’b 00: outc = a; 2’b 01: outc = b; 2’b 10: outc = c; default: outc = d; endcase; P 31

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU if-then-else Statement v An if-then-else statement infers a priority-encoded, cascaded combination of multiplexers. if (sel == 2’b 00) outi = a; else if (sel = 2’b 01) outi = b; else if (sel = 2’b 10) outi = c; else outi = d; P 32

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU case vs. if-then-else Statements v case statements are preferred if the priority-encoding structure is not required v The multiplexer is faster. v if-then-else statement can be useful if you have a latearriving signal v Connect the signal to a in last slide v A conditional assignment may also be used to infer a multiplexer. assign z = (sel_a) ? a : b; P 33

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Outline v Principles of RTL Coding Styles v v Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis v Debugging Tool: n. Lint P 34

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Register All Outputs v For each subblock of a hierarchical macro design, register all output signals from the subblock. v Makes output drive strengths and input delays predictable P 35

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Related Combinational Logic in a Single Module v Keep related combinational logic together in the same module clk R 1 ABC B clk C clk R 2 Better R 2 R 1 Bad ABC clk R 2 Best P 36

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Outline v Principles of RTL Coding Styles v v Readability Finite state machine (FSM) Coding for synthesis Partitioning for synthesis v Debugging Tool: n. Lint P 38

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU GUI v n. Lint -gui & P 39

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Import Design P 40

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Edit File P 41

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Lint -> Run P 42

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Fix Warning 1 P 43

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Search Rule v Right click -> Search Rule P 44

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU No Error & Warning P 45

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Check for Synthesizable (1/2) v Spring. Soft n. Lint v Check for correct mapping of your design v Not so power in detecting latches v Synopsys Design Compiler v Synthesis Tool v The embedded Presto Compiler can list your flip-flops and latches in details > dv -no_gui > read_verilog yourdesign. v P 46

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Check for Synthesizable (2/2) Checking latches using Design Compiler P 47