Goals Look at two word synchronization techniques Look

Goals • Look at two word synchronization techniques. • Look at signal integrity of LVDS transmission at receiving end of 34’ cable for 177 Mbps and 139 Mbps data rates. • Determine if DC balancing cable is necessary. • Quantify timing margins based on measured results and assumptions. B. Hall June 14, 2001 Pixel Readout 1

Word Sync Method A B. Hall June 14, 2001 Pixel Readout 2

Word Sync Method A Implementation of Word Sync Method A with DC balancing: With RCLK = 34. 72 Mhz, SCLK = 173. 6 Mhz (~174 Mbps serial links) B. Hall June 14, 2001 Pixel Readout 3

Word Sync Method A Implementation of Word Sync Method A with NO DC balancing: With RCLK = 34. 72 Mhz, SCLK = 138. 88 Mhz (~139 Mbps serial links) B. Hall June 14, 2001 Pixel Readout 4

Word Sync Method A • Simple to Implement • Receiver FPGA looks for leading ‘ 1’ to mark word boundaries. • FPGA can check for out of sync signs: illegal column address, more or less than 24 (or 30 in DC balance case) bit long words. • FPIX should transmit a sync word while data out of the core is idle. • Will need handshaking protocol allowing the receiver FPGA to request sync word transmission from FPIX. B. Hall June 14, 2001 Pixel Readout 5

Word Sync Method B B. Hall June 14, 2001 Pixel Readout 6

Word Sync Method B • A bit more complicated to implement: B. Hall June 14, 2001 Pixel Readout 7

Word Sync Method B 6 serial lines would look like: B. Hall June 14, 2001 Pixel Readout 8

Word Sync Method B One serial line configuration: B. Hall June 14, 2001 Pixel Readout 9

Word Sync Method B • More logic required to implement. • Word sync every word…very fast recovery from transmission errors…should be very robust. • Must use 30 bits per word… 177 Mbps serial links. • Encoding also DC balances by allowing no more than 4 consecutive 0 s or 1 s (with NRZI). B. Hall June 14, 2001 Pixel Readout 10

Signal Edge Skew Sources B. Hall June 14, 2001 Pixel Readout 11

Data Edge Skew Sources B. Hall June 14, 2001 Pixel Readout 12

Skew Due to Cable Charging • Use 34’ pleated foil flat cable (baseline for pixel system). • Inject LVDS signal at 177 Mbps and 139 Mbps. • Use pattern generator to transmit pattern with no DC balancing (up to 23 seq 0 s or 1 s) or a pattern with DC balancing (up to 4 seq 0 s or 1 s). • Look at received (LVDS to 3. 3 V CMOS) data and measure the signal edge movement due to cable charging. B. Hall June 14, 2001 Pixel Readout 13

Cable Charging – 177 Mbps No DC Balance B. Hall June 14, 2001 Pixel Readout 14

Cable Charging – DC Balance: upto 4 seq 0 s or 1 s B. Hall June 14, 2001 Pixel Readout 15

Cable Charging – 139 Mbps No DC Balance B. Hall June 14, 2001 Pixel Readout 16

Cable Charging – 139 Mbps DC Balance: upto 4 seq 0 s or 1 s B. Hall June 14, 2001 Pixel Readout 17

Cable Charging Conclusions • With 34’ cable @ 177 Mbps or 139 Mbps, DC balancing not critical. • @177 Mbps and No DC balancing: skew = 2. 53 ns • @177 Mbps and DC balancing: skew = 2. 33 ns • @139 Mbps and No DC balancing: skew = 1. 69 ns • @139 Mbps and DC balancing: skew = 1. 69 ns B. Hall June 14, 2001 Pixel Readout 18

Other Contributions • FPIX pad to pad delay: 250 ps (assumption) • Feedthrough board: 0 ns (assumption) • Cable propagation delay variation (pair to pair): 1. 3 ns (previous study) • Cable charging: 1. 69 ns (@139 Mbps, DC Balanced or not), 2. 53 ns (@177 Mbps, No DC Balance), or 2. 33 ns (@177 Mbps, DC Balanced up to 4 seq 0 s or 1 s) • Data combiner board: 0 ns (assumption) • FPGA pin to pin delay: 250 ps (assumption) • FPGA latch setup requirement: 800 ps (Specification). B. Hall June 14, 2001 Pixel Readout 19

Timing Margins (Clock Sampling Window) • With 177 Mbps and No DC Balancing: 520 ps • With 177 Mbps and DC Balancing (4 seq): 720 ps • With 139 Mbps and No DC Balancing: 2. 9 ns • With 139 Mbps and DC Balancing (4 seq): 2. 9 ns Also need to consider jitter of the clock itself. B. Hall June 14, 2001 Pixel Readout 20

Conclusions/Discussion • 177 Mbps has a good chance of not working. • 139 Mbps has a good chance of working. • FPIX multiple serial line skew should be as tight as possible. • Word sync method A (leading 1 technique) will have to be used for 6 serial line configuration with 139 Mbps. • Word sync method B (leading “ 00011” technique) can still be used for 1, 2, or 3 serial line configurations (@139 Mbps). B. Hall June 14, 2001 Pixel Readout 21