Global Trigger Global Muon Trigger ClaudiaElisabeth Wulz Anton
Global Trigger Global Muon Trigger Claudia-Elisabeth Wulz Anton Taurok Institute for High Energy Physics, Vienna Hannes Sakulin CERN Annual Review CERN, 24 Sep. 2001
URL’s This talk may be found at: http: //wwwhephy. oeaw. ac. at/p 3 w/cms/trigger/global. Trigger/trans/wulz_Ann. Rev_sep 01. ppt More detailed transparencies prepared by H. Sakulin about the Global Muon Trigger may be found at: http: //wwwhephy. oeaw. ac. at/p 3 w/cms/trigger/global. Muon. Trigger/trans/ GMT-Int. Review 24 Sep 2001. pdf More detailed transparencies about the Global Trigger prepared by A. Taurok and presented at the Trigger Meeting on Tuesday, 25 Sep. 2001, may be found at: http: //wwwhephy. oeaw. ac. at/p 3 w/cms/trigger/global. Muon. Trigger/trans/ GT_GTM_status_Sept 01. ppt General information about the Global Trigger and the Global Muon Trigger is available at: http: //wwwhephy. oeaw. ac. at/p 3 w/cms/trigger/global. Trigger http: //wwwhephy. oeaw. ac. at/p 3 w/cms/trigger/global. Muon. Trigger Claudia-Elisabeth Wulz 2 Annual Review, 24 Sept. 2001
Global Trigger Environment Claudia-Elisabeth Wulz 3 Annual Review, 24 Sept. 2001
Board Layout of the Global Trigger Processor PSB (Pipeline Synchronizing Buffer) GTL (Global Trigger Logic) FDL (Final Decision Logic) TCS (Trigger Control System Module) NEW: L 1 A (Level-1 Accept Module) TIM (Timing Board) GTFE (Global Trigger Frontend) Claudia-Elisabeth Wulz 4 Input synchronization Logic calculation L 1 A decision Trigger Control Delivery of L 1 A Timing Readout Annual Review, 24 Sept. 2001
Global Trigger 9 U Crate (old) Claudia-Elisabeth Wulz 5 Annual Review, 24 Sept. 2001
Global Trigger 9 U Crate Claudia-Elisabeth Wulz 6 Annual Review, 24 Sept. 2001
Global Trigger Rack Claudia-Elisabeth Wulz 7 Annual Review, 24 Sept. 2001
Global Trigger Progress and Milestones ¨Milestone March 2002: System Test This includes the backplane, the PSB-6 U, GTL-6 U, FDL-9 U and TIM-9 U. The GTFE and the GMT are not included. 4 Backplane-6 U: Prototype available 4 PSB-6 U: available. Channel Link receivers used. • GTL-6 U: Automatic chip design and setup procedure developed. Layout for a 20 channel GTL (4 , 4 isol. e/ , 4 central jets, 4 fwd jets, SET, ETmiss, 8 jet multiplicities; other quadruplets can be connected alternatively for tests) is currently being finished. 1020 -pin Altera FPGA 20 k 400 E included for evaluation. The layout of a conversion board to be used later in final 9 U-crate is ready. It contains also memories in FPGA’s to send simulated test data to the GTL-6 U board. • FDL-9 U: Design with 8 final OR’s in progress. • TIM-9 U: The design of the board is nearly finished. The board contains a TTCrx chip and provides all timing signals for the GT crate. It will be used also in the Drift Tube Track Finder crates. An FPGA provides all necessary test functions to run the crate without the central TTC clock. It simulates also L 1 A requests for monitoring or to test the readout chain. Claudia-Elisabeth Wulz 8 Annual Review, 24 Sept. 2001
Global Trigger Progress and Milestones ¨Milestone July 2002: TCS-9 U ready • TCS-9 U: The main functions are defined but the design is still open for additional requests (calibration logic etc. ) Trigger Partitions: The maximum number of subsystems is fixed (32). A preliminary agreement about the output to the DAQ Event Manager is has been reached. The input format of Fast Signals should be fixed soon. 5 coded bits per subsystem, sent as parallel data, are proposed. The TCS board provides data for the standard TTCvi as well as for a ”CMSTTCvi”, but different interface boards are required. L 1 A driver module to be used with CMS-TTCvi has been conceived. Claudia-Elisabeth Wulz 9 Annual Review, 24 Sept. 2001
Global Trigger Progress and Milestones ¨Milestone October 2002: 9 U backplane ready The design with the GTLp 80 MHz and Channel Links is in progress. ¨Milestone June 2003: Complete GT prototype available Integration tests possible from this date. • GTFE-9 U: Conceptual design of readout board done. ¨Milestone July 2004: 12 -channel PSB-9 U available • PSB-9 U: Conceptual design done. Will have memories inside FPGA’s. ¨Milestone Nov. 2004: Complete GT available Includes GTL-9 U module with all 32 input channels (4 , 4 isol. e/ , 4 non-isol. e/ , 4 central jets, 4 forward jets, 4 t-jets, SET, ETmiss, 8 jet multiplicities). The Global Muon Trigger will have been completed by Nov. 2003. Claudia-Elisabeth Wulz 10 Annual Review, 24 Sept. 2001
Global Muon Trigger DTBX RPC Calo. Trigger CSC BTI CAL Readout Warsaw TRACO PACT Wisconsin Track Correlator Pattern Comparator Regional CALO Trigger GLOBAL Bristol CALORIMETER TRIGGER Bunch & Time ID RPC Strip cards Pipelined Motherboard Trigger Server DT MIP & quiet bits (2 x 252) Wire cards Bari HEPHY Vienna Barrel Track Finder DT Sorter Bologna Sorter 4+4 40 MHz CSC Florida Endcap Track Finder CSC Rice Sorter HEPHY Vienna GLOBAL MUON TRIGGER HEPHY 4 Vienna GLOBAL L 1 TRIGGER L 1 Accept ………… Claudia-Elisabeth Wulz 11 max. 100 k. Hz Annual Review, 24 Sept. 2001
Tasks and Location of the Global Muon Trigger ØReceive Muon Candidates from DT, CSC and RPC Triggers ØFind the best 4 muons in the detector ðMake use of the complementarity of the muon trigger systems (DT/RPC barrel, CSC/RPC endcap) à increase efficiency à reduce ghosts à reduce trigger rate by improving p. T assignment ØAdd MIP and Quiet bits from the calorimeter trigger ØForward best 4 muons to the Global L 1 Trigger ØGMT is located in the GT crate. It consists of 3 input boards (PSB) for the calorimeter information and 1 logic board. 3 additional slots used due to connectors. Claudia-Elisabeth Wulz 12 Annual Review, 24 Sept. 2001
Principle of the Global Muon Trigger • Inputs: 8 bit f, 6 bit h, 5 bit p. T, 1 bit charge, 3 bit quality • Further Inputs: MIP and Quiet Bits of 252 calorimeter regions 3 programmable merging modes: winner/loser parameter selection parameter mixing • Output: 8 bit f, 6 bit h, 5 bit p. T, 1 bit charge, 3 bit quality, 1 bit MIP, 1 bit Isolation Responsible: H. Sakulin, A. Taurok, C. -E. Wulz Claudia-Elisabeth Wulz 13 Annual Review, 24 Sept. 2001
Global Muon Trigger Schedule Ø Milestones / Plans: ð 2001 Logic design, ORCA + VHDL Simulation l Dec 2001 Logic design finished ð 2002 VHDL Simulation, Design of FPGA chips l Dec 2002 FPGA design finished ð 2003 Production of VME 9 U Boards ð 2004/05 Integration tests, production of spare boards Claudia-Elisabeth Wulz 14 Annual Review, 24 Sept. 2001
Progress towards GMT milestones Ø Dec 2001: Logic design finished ü Progress in detailed logic design • Chip Models selected (mostly Virtex II), interconnections defined • Design compacted (external RAMs moved into big FPGAs) ü Improvement of functionality • DT/CSC cancel-out unit (improved performance in barrel/endcap overlap region) ü in parallel: • ORCA simulation extended and improved • Continuous studies to optimize GMT design parameters and performance – CMS Note 2001/003 published: H. Sakulin, M. Fierro, “Studies of the Global Muon Trigger Performance” ð Detailed GMT design document in preparation ð VHDL behavioral level simulation has started Ø Dec 2002: FPGA design finished ü FPGA models have been selected ð Synthesis tools are being evaluated Claudia-Elisabeth Wulz 15 Annual Review, 24 Sept. 2001
New: GMT solution with 1 logic board Claudia-Elisabeth Wulz 16 Annual Review, 24 Sept. 2001
Simulation - muon 2001 production Claudia-Elisabeth Wulz 17 Annual Review, 24 Sept. 2001
GMT single muon trigger rates (p. T > 16 Ge. V/c) Simulation - muon 2001 production ORCA 5. 1. 2 Ø GMT optimized as in ORCA 5. 1. 2 ð rate at 20 Ge. V/c: 3. 1 k. Hz ð L 1 efficiency(*): 96. 6 % Rate from unconfirmed 2 -station CSC tracks re-tuned GMT Ø re-tuned GMT selection: ð Only three-station CSC tracks used without RPC confirmation ð rate at 20 Ge. V/c: 1. 4 k. Hz ð L 1 efficiency(*): 96. 3 % h Claudia-Elisabeth Wulz (*)efficiency 18 sample to find muon of any p. T in flat p. T Annual Review, 24 Sept. 2001
L 1 efficiency with retuned GMT ORCA 5. 1. 2 re-tuned Efficiency/% GMT efficiency to find any muon in a flat p. T sample as in ORCA 5. 1. 2 w/o RPC noise eff= 96. 6% eff= 96. 3 % Efficiency contribution from CSC Q 2 muons (lost with re-tuning) Claudia-Elisabeth Wulz 19 Annual Review, 24 Sept. 2001
Single muon rates Ø Trigger rate at 20 Ge. V/c (re-tuned GMT) ð 1. 4 k. Hz (last year: 2. 9 k. Hz) Ø Generated rate at 20 Ge. V/c ð ~120 Hz (last year: ~200 Hz) Claudia-Elisabeth Wulz 20 Annual Review, 24 Sept. 2001
Dimuon rates Claudia-Elisabeth Wulz 21 Annual Review, 24 Sept. 2001
Single muon and dimuon trigger rates Claudia-Elisabeth Wulz 22 Annual Review, 24 Sept. 2001
GT and GMT Manpower ¨System Engineer: A. Taurok ¨CERN Doctoral Student: H. Sakulin (Logic and Hardware Design of GMT) ¨Technicians: (shared with DTTF and other activities) H. Bergauer, M. Padrta, K. Kastner (in Vienna) Ch. Deldicque (at CERN) ¨Physicists: M. Fierro, A. Jeitler, C. -E. Wulz (mainly working on GT/GMT) N. Neumeister, P. Porth, H. Rohringer, L. Rurua (partly working on other activities) L. Boldizsar (GT simulation, about 4 months per year in 2001 and 2002) Claudia-Elisabeth Wulz 23 Annual Review, 24 Sept. 2001
Conclusions Ü Progress in hardware design as planned Ø Global Trigger: Layout of GTL-6 U almost ready Timing module designed Other modules also on track Design of TCS system updated Ø Global Muon Trigger: FPGA chips selected Design compacted New solution with one logic board VHDL simulation has started Claudia-Elisabeth Wulz 24 Annual Review, 24 Sept. 2001
Conclusions Ü New simulation results with muon 2001 production for Global Muon Trigger Øp. T-cut was lower than in last year’s production Øimproved CSC trigger & GMT can cope with higher background rate Øtrigger rates with improved trigger are lower despite higher background (even after taking into account the changed sample normalization) Claudia-Elisabeth Wulz 25 Annual Review, 24 Sept. 2001
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