Getting Started with Vivado Tutorial 2 1 Vivado

Getting Started with Vivado Tutorial 2 1

Vivado typical design flow 2

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The target device choosing (xc 7100 csg 324 -1) 6

The next section gives a summary of the options selected throughout the wizard. Verify that the information looks correct and click Finish 7

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sum <= a xor b ; carry <= a and b ; 14

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2 1 architecture bench of Half. Adder_source_beh_tb is component Half. Adder_source_beh Port ( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end component; signal a_tb: STD_LOGIC; signal b_tb: STD_LOGIC; signal sum_tb: STD_LOGIC; signal carry_tb: STD_LOGIC; begin uut: Half. Adder_source_beh port map ( a => a_tb, b => b_tb, sum => sum_tb, carry => carry_tb ); stimulus: process begin a_tb <= '0' ; b_tb <= '0' ; wait for 10 ns; a_tb <= '0' ; b_tb <= '1' ; wait for 10 ns; a_tb <= '1' ; b_tb <= '0' ; wait for 10 ns; a_tb <= '1' ; b_tb <= '1' ; wait for 10 ns; wait; end process; 21 end bench;

https: //www. doulos. com/knowhow/perl/testbench_creation/ 22

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Tutorial Lab. Structure of six different gates a => sw(1), b => sw(0), z => ld 36

Tutorial Lab Schematic after synthesis 37

Schematic – elaborated design 38

library IEEE; use IEEE. STD_LOGIC_1164. ALL; entity gates 2 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; z : out STD_LOGIC_VECTOR (5 downto 0)); end gates 2; architecture Behavioral of gates 2 is begin z(5) <= a and b; z(4) <= a nand b; z(3) <= a or b; z(2) <= a nor b; z(1) <= a xor b; z(0) <= a xnor b; end Behavioral; 39