General Presentation on IMECs Thematic Design Activities Ivo

General Presentation on IMEC’s Thematic Design Activities Ivo Bolsens, Hugo De Man + 125 researchers bolsens@imec. be 1 © 2001

IMEC organization CEO: Gilbert Declerck Divisions DESICS: design technology Ivo Bolsens SPT: process technology Luc van den Hove STDI: silicon techn. & device integration Herman Maes MCP: microsystems & packaging Robert Mertens INVOMEC: training Etienne Bourdeaud’hui 2 © 2001

Mission Design of Architectures, Methods and Tools for the Implementation of Multimedia Internet Terminals 3 © 2001

How • Study requirements of embedded IT systems • Identify and solve RELEVANT design challenges - build application demonstrators • Work out systematic design methods and supporting tools - build tools for real-life design support • Develop re-usable, parameterized, white-box IP • Train and educate - industry - university 4 © 2001

Measures of success • scientific impact • cooperation with universities in complementary fields • international network of cooperation with most of the important industrial performers in our field • portfolio of protected intellectual property • transfer of technologies to existing companies • creation of new spin-off companies • attracting foreign investments in the field of microelectronics and ICT • turn-over of well trained researchers to industry 5 © 2001

Bridge the gap between systems and silicon Systems Heaven a JAVA, CORBA, JINI 5 million lines of VHDL 0. 1µm =1/300 Hair 200 M Transistors 6 Physics Hell Power/ cm**2 ~ V**3/l**3 T_intercon ~ r *l**2/l**2 © 2001

Intelligent Home 155 Mb/s WLAN 5 GHz 10 Gop/s W W W 7 Reconfigurable Access Terminal <1 Watt MPEG 4 >100 Gop/s 5 Gtr/s 5 Watt © 2001

DESICS organization DIMA: design of integrated multimedia applications • MICS: multimedia image compression systems • EMSYS: embedded systems design • SEMP: system exploration for memory & power DISTA: design of integrated systems for telecom applications • MIRA: • WISE: mixed signal & RF applications wireless systems • DBATE: digital broadband terminals 8 © 2001

Configurable Home Terminal Head End Home gateway HFC Service Server router storage basestation IPv 6 IP Home network modem CSL Internet home Appliance 9 User premises © 2001

Embedded connectivity Distributed Application Middleware RPC Middleware OS packets OS Hardware signals Hardware 250 W, 700 MHz, 128 MByte 10 2 W, 30 MHz, 256 Kbyte PLUG&PLAY VCR © 2001

Challenges Reconfigurable Software Agent VM TCP/IP RTOS user data CTL MON Digital software agents parameters & synchro Front Tx/Rx End DSP Analog 11 CFIL/CB To I/O Hardware © 2001

Challenges in Dynamic Reconfiguration Run-time FPGA management • dynamical creation and deletion of HW processes • dynamical creation of the related HW/SW interfaces • dynamical extension of the instruction set - downloading of FPGA configuration for additional instruction Fast HW compilation Novel FPGA architectures optimized for partial runtime configuration Performance Estimation (dynamic, configuration time) 12 © 2001

Networked re-configurable computing Application Layer (Java applet +FPGA bitstream) Middleware Layer FPGA API FPGA Controller Real-Time Operating System Java Native Interface Virtual Bus Hardware Platform Native Device Driver Local Bus Software 13 FPGA Hardware © 2001

The first demonstrator: FPGA based Net. Cam Internet Client Ibis CMOS sensor ATMEL EEPROM Netscape HTTP IP layers 10 Base T GIF Engine request image network Reconfiguration FPGA TCP/IP layers 10 Base T • first FPGA-based “thin-server” Internet Appliance 14 (vs. Dedicated, Linux or u. C based) • low power (FPGA ~ 0. 7 W) • throughput scales up to 80 Mb/s © 2001

World’s first 80 MB/sec WLAN technology wired backbone Base station 155 Mb/s multi-user rx antenna diversity Multi-path fading • Orthogonal Frequency Division Multiplexing (OFDM) 15 • Turbo-coding • Spatial Division Multiple Access (SDMA) • Hiperlan-2/ IEEE 802. 11 compatible © 2001

Single-package transceiver CMOS: IF and digital circuitry Bi. CMOS: R F circuitry MEMS: switches, varactor, resonators MCM: interconnect Antenna 16 inductors, capacitors, resistors, filters, baluns © 2001

Multimedia : MPEG-4 member SCtee - Diversity : 3 D, Facial and Body Animation, Video - Scalability : time, space, SNR - Interactivity : behaviour = f (input bits, user) 17 © 2001

Focus • Graceful degradation, QOS • Encode once/ decode everywhere • Reduces the terminal cost (“soft” conformance with pathological cases) • Man-Machine Interface : Facial Animation • Real-time SOFTWARE video-coding of CIF images • Application Specific Processor for Wavelet coding Demo 18 © 2001

Challenges Nowadays Multimedia: implementations: MPEG 4 JPEG 2000 small images (QCIF: Several orders of magnitude in 176 x 144) Huge requirements: decoding only performance and dissipation >power 2 GOP/s need tonot be gained > 6 real-time GB/s several W storage > 10 MB Software specification: Drastic. Wanted reduction of design features: more than 200 000 lines C complexity required large images (TV) hundreds of decoding files encoding and written by approx. 80 teams real-time 100 m. W (mobile) 19 © 2001

World’s first MPEG-4 compliant silicon Max 30 fps CIF (352 x 288) Scalable architecture 20 © 2001

C/C++ system refinement + exploration Algorithms + Data Structures Architecture ARM IP 1 RAM ROM IP 2 Processor architecture ROM custom logic micro processor MMU 21 RAM DSP © 2001

Deeply embedded system Interfaces Dedicated logic RAM & ROM phone book DMA book S/P Demod and sync control keypad intfc protocol Equal. speech quality enhancement D digital down conv • accelerator synthesis multi-DSP core • retargetable ASIP compiler Memory/MMU Interfaces Viterbi A P core Dedicated logic de-intl & decoder voice recognition • system integration Analog RPE-LTP speech decoder Multi-DSP core All of this fits in one, cheap, package 22 © 2001

Deeply embedded system P core Memory/MMU RAM & ROM P core DMA keypad control protocol book S/P Demod and sync phone book intfc • Dedicated logic multi-DSP core memory/MMU • Viterbi Equal. speech quality enhancement A D digital down conv de-intl & decoder voice recognition RPE-LTP speech decoder system layer compiler dynamic + static mem mngnt + addr expr. Interfaces Analog • A/D + RF Analog All of this fits in one, cheap, package 23 © 2001

Current challenges and solutions • System Specification and System-level Refinement with Exploration Support (algorithm design level, concurrent task level, system timing simulation) Tipsy, Matisse-TCM • Data Transfer and Storage Exploration for Massive Real Time Data Manipulation (dynamic memory mngnt static transfer and storage, address generation) Matisse-DMM, Atomium/Acropolis, Adopt • Co-Design for Heterogenous Implementation Paradigms (refinement from unified HW/SW model, RTOS modeling, complete system simulation) Ocapi-2, So. Cos • RF front-end exploration (fast mixed-signal cosimulation, chip-package co-design, noise coupling) 24 Fast © 2001

So. C or …---… (S. O. S. ) Design productivity gap grows ! • Complexity increase 40 % per year • Design productivity increase 15 % per year [ 106 T/chip ] 250 200 150 100 50 1995 1998 2001 2004 2007 [ SIA roadmap ] 25 © 2001

System-level design Solution • Paradigm shift - Higher abstraction level - Executable specs - Object-oriented design - Multi-paradigm modeling - Behavioral IP re-use - Incremental refinement to RT-HDL (HW) and C/C++ (SW) 26 © 2001

System design issues in IT-Application domain OUT 622 Mb/s ISR data in IN 622 Mb/s Packet Record time out FIFO Routing Record routing reply data out 200 accesses 53 cycles OUT 622 Mb/s Embedded system Processes • Dynamic and concurrent processes • Global/local control • Little arithmetic/ logic processing Complex data sets • Large and irregular dynamically allocated data • Huge memory accesses Stringent real-time constraints Network layer protocols (ATM, IP, …) E. g. : Multi-media algorithms with dynamic character (MPEG 4, MPEG 7) 27 Wireless and wired terminals (Internet, WLAN, ADSL, …) © 2001

Global concurrency management design flow for dynamic concurrent tasks with data-dominated behaviour Concurrent OO spec Dynamic memory mgmt Task concurrency mgmt Task 2 Task 1 Transform Task schedule Allocate/assign Task 3 Physical memory mgmt Address optimization SW/HW co-design 28 SW design flow HW design flow Memory organ. Unified model Partition Refine/compile HW DSP u. Proc HW-Ctrl u. Ctrl System control © 2001

TCM steps aim at removing the bottlenecks for better performance Task 1 1 3 Task 2 Optimized system specification Inter-task DTSE 2 Task concurrency mngnt Task 3 Virtual Proc 1 Virtual Proc 2 Task conc. Extraction/trafo 1 2 Task/thread scheduling 2 Proc Array-processor allocation Task to processor assignment Inter-task interface refinement Task-level system architecture 29 © 2001

The gray box approach focuses on the most relevant TCM issues Black-box TCG 1% Improved Gray-box <10% Initial gray-box TCG 10% Initial TCG 50% High Level Specification task concurrency extraction & improvement Reduce complexity Create freedom Simplify the model 30 White-box TCG 100% C++ Specification © 2001

Task Level DTSE and TCM grey-box model specification Task level DTSE concurrency extraction/ improvement static scheduling (partial ordering) dynamic scheduling 31 © 2001

Results on IM 1 player Cost x x 32 Time-Budget (MA cycle budget) © 2001

The 2 -processor approach (scheduling + assignment) Task 1 33 Task 2 Taskn ARM Processor 1 Vdd=1 V 2 Vdd=3. 3 V © 2001

Comparison of scheduling the original and transformed graphs original Transformed 34 © 2001

Combination of static and dynamic scheduler Static Scheduling 1 3 2 Static Scheduling Dynamic Scheduling A B 1 A B 3 2 Static scheduling: done at compiling time, exploring all the optimization possibility Dynamic scheduling: done at run time, providing flexibility and dynamic control at low cost 35 © 2001

Dynamic Scheduling result total energy 39% 32% 24% 20% node number in timer threads Two Proc. (vlow = 1 V, vhigh = 5 V) One Proc. (v = 5 V) 36 © 2001

So. C refinement and exploration • Implementation • System requirements - Abstract functionality - Final hardware - Target platform constr. - OS services optimized for application - Appl. software - Real-time constraints So. C appl. + timing Memory mgmt constr. Process mgmt constr. Target platform 37 R E Q U I R E M E N T R E A L Application implementation (HW/SW) Memory mgmt impl. (HW/SW) Process mgmt impl. (HW/SW) Final platform (Silicon) © 2001

Refinement and exploration Memory mgmt • Dynamic memory - alloc / free (C) - new / delete (C++) - abstract data type refinement - virtual memory mgmt • Static memory - platform-independent code transformations - real-time cost-optimal physical memory organisation • Address optimisation 38 Process mgmt • Task level concurrency mgmt (platform indep. ) - transformations - static/dynamic scheduling - resource allocation • Instruction-level concurrency mgmt - refinement from unified HW/SW model - RTOS modeling/simulation including timing - traditional HW/SW co-design and compilers © 2001

Refinement - OCAPI / MATISSE • Implementation • Virtual prototype - Target hardware - Soft implementation using host OS and host hardware - OS services optimized for application So. C appl. + arch. Memory mgmt Process mgmt OSAPI Host HW (HP/PC) 39 V I R T U A L R E A L Application implementation (HW/SW) Memory mgmt impl. (HW/SW) Process mgmt impl. (HW/SW) Target HW (Silicon) © 2001

Unified Modeling and Refinement of HW and SW OCAPI-xl C++ Class Lib Flexible Primitives express High Level System Model unified HW/SW model Refined Model 40 • Concurrency • Communication • Interface design/reuse Built-in Code Generators create • VHDL/Verilog/C • Testbenches © 2001

So. C++ design flow C++ System Model HW FSMD SW OSAPI Code Generation HDL/System. C C System Link & Interface Synthesis 41 © 2001

System Model HW FSMD SW OSAPI Code Generation HDL/System. C C System Link & Interface Synthesis 42 © 2001

Global data management design flow for dynamic concurrent tasks with data-dominated behaviour Concurrent OO spec Dynamic memory mgmt Task concurrency mgmt Physical memory mgmt Address optimization SW/HW co-design 43 SW design flow HW design flow Abstract Data Types Virtual Memory Mgmt Memory Allocation Assignment Memory Mgmt Unit Binary Tree (BT) key data Free Blocks Sub-pool per size processor mem mem ASU controller © 2001

Data Management Flow ADT Abstract Data Type (ADT) Refinement Concrete Data types Virtual Memory Segments Virtual memory mgmt (VMM) Refinement Dynamic Memory Mngnt. Physical memory mgmt (PMM) Refinement Physical Memories 44 Physical Memory Mngnt. © 2001

Matisse: ADT refinement Binary Tree (BT) ATM_cell * Data_In; Association_Table * Routing_Table; Array Binary_Tree * Routing_Table; Linked_List ** Routing_Table; key data Routing_Table = new Association_Table(); Array (); Binary_Tree (); Linked_List (); Data_In = new ATM_cell(); key data if ( Routing_Table->Lookup(Data_In) ). . . data Power function data Array (AR) Linked List (LL) key data 45 key data Area function 10 4 10 3 10 2 10 1 10 0 Impl. alternatives © 2001

ADT refinement results Select best DT impl. for each ADT LL(A) LL(B) Power cost function 104 103 102 PA(A) AR(B) PA(B) BT(A) PA(B) LL(A) 101 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Different data types 46 © 2001

PA(9) AR(4) 2 VMS Size = 137 mm 2 Power = 68 m. W AR(4) 2 VMS Size = 137 mm 2 Power = 49 m. W 32 PA(9) PA(5) 256 256 47 PA(9) PA(5) AR(4) 1 VMS Size = 133 mm 2 Power = 110 m. W 32 PA(5) AR(4) PA(5) 256 32 PA(9) PA(5) 32 VM size for ATM MUX in network 1 AR(4) 3 VMS Size = 137 mm 2 Power = 37 m. W © 2001

Memory = CPU Performance Bottleneck Performance µProc: 60%/year. 1000 CPU 100 Processor-Memory Performance Gap: (grows 50% / year) “Moore’s Law” 10 DRAM: 7%/year DRAM 1 1980 1985 1990 Time 1995 2000 [Patterson] 48 © 2001

Data-transfer and data-storage bottlenecks: SDRAM access Client 128 - 1024 Cache bit bus and Bank data comb. Wide word 49 Main Memory Local Latch bank 1 Local Select Local Latch bank. N Select Local Global Bank Select Control ctrl addr Burst mode © 2001

Data-transfer and data-storage bottlenecks: cache misses Data-paths Processors regf Client Main Memory 16 k. B N-port SRAM 1 MB 1/2 -port SRAM L 1 cache L 2 cache Main Memory 256 MB (S)DRAM Many cache misses Page Loading 50 © 2001

Data-transfer and data-storage bottlenecks: system bus load Main system bus L 2 bus Data paths L 1 cache L 2 cache Main Memory Disk access bus Hard disk System chip Other System Resources 51 Other System Resources © 2001

Memory = Power Bottleneck DP MMU SRAM PROC SRAM Embedded EXTERNAL MEMORY DRAM P(Ext. Access) = typ. 30 x P(Arithmetic Operations) P(Int. Memory) = typ. 40 % - 60 % P(Chip) 52 © 2001

Multi-processor System Design Locally optimized Image Proc System Globally optimized => exploration! Standard subsystem : detailed solution locally optimized by expert E. g. : 2 D convolution 53 New complex subsystem Buffer E. g. : quadtree coder Subsystem resembles a standard solution but needs small adaptations E. g. : DCT for specific coder © 2001

Platform design requires change (multi-media) = Power volcano processor trend Application engineer Traditional compiler boulevard Multi-media platform city Traditional architecture city Cobblestone bypass road (requires paving) 54 © 2001

Data Transfer & Storage Principles 4 Avoid N-port Memories Processor L 1 L 2 Data Paths Cache & Bank Recombine Chip Local Latch 1 + Bank 1 Local Latch N + Bank N Off-chip SDRAM 2 Introduce Locality 1 Reduce redundant transfers 6 Exploit limited life-time and data layout freedom 55 3 Exploit memory hierarchy 5 Meet real-time constraints © 2001

Pareto curves allow task trade-off decision: DAB illustration TASK-1 TASK-2 E ner g y 1000 TASK-3 12 15 8 10 4 5 500 0 0. 0 2. 0 4. 0 6. 0 Execution time 0 0 10000 20000 30000 Execution time 40000 0 0 50000 100000 Execution time Mapped on two processors 56 Source: Digital Audio Broadcast © 2001

Pareto curves allow task trade-off decision TASK-1 TASK-2 E ner g y 1000 TASK-3 12 15 8 10 4 5 500 0 0. 0 2. 0 4. 0 6. 0 Execution time 0 0 10000 20000 30000 Execution time 40000 0 0 50000 100000 Execution time Single proc. Large mem. overhead 57 Source: Digital Audio Broadcast © 2001

Pareto curves allow task trade-off decision TASK-1 TASK-2 E ner g y 1000 15 8 10 4 5 500 0 0. 0 2. 0 4. 0 6. 0 Execution time 58 TASK-3 12 0 0 10000 20000 30000 Execution time 40000 0 0 50000 100000 Execution time Source: Digital Audio Broadcast © 2001

Cavity Detection Algorithm on Intel Pentium-MMX (+execution time) 59 © 2001

Resource limited software Factor 12 bus load reduction Factor 5 power reduction Factor 3. 5 performance increase Percentage (%) TRIMEDIA processor 100 90 80 70 60 50 40 30 20 10 0 Exec Time Initial Algorithm 60 Power Bus Load DTSE Transformed © 2001

Voice coder (SW cache): full power summary Relative power Cache Power 2 Main memory Power 1 0 32 w 64 w 96 w 128 w 256 w 512 w Cache Size [ words ] Gain in power of additional factor 6 compared to optimized (platform independent code) 61 © 2001

MPEG - 4 Motion Estimation 1. 0 Task Level DTSE Processor Level DTSE Search Area memories VOP memories Relative Power Total Memory Power 0. 5 0. 0 Optimizations steps Resulting Power Reduction = 8 62 © 2001

Consistent Speed Up on Different Platforms for MPEG 4 video decoder Framerate (frames/second) Performance of PI MPEG-4 Video Decoder on Different Platforms 63 120. 0 Pentium II 350 MHz HP PA RISC 180 MHz Tri. Media 100 MHz 100. 0 80. 0 60. 0 40. 0 20. 0 M & D CIF 120 kbps 30 fps Foreman CIF 450 kbps 25 fps Cal & Mob CIF 2 Mbps 30 fps © 2001

Remaing Power (%) Power Reduced with Factor 21 to 48 5. 0 4. 5 4. 0 3. 5 3. 0 2. 5 2. 0 1. 5 1. 0 0. 5 0. 0 Assesment Memory Power Reduction (Proprietory Architecture) M & D CIF 120 kbps 30 fps 64 Foreman CIF 450 kbps 25 fps Cal & Mob CIF 2 Mbps 30 fps © 2001

Turbo coding principle Encoder Decoder Û U C 1 Y D 1 D 2 -1 C 2 65 C © 2001

Results Original: bit-rate: 0. 07 Mbit/s power: 1. 07 J/bit latency: 5900 s area: 3. 5 mm 2 optimizations 66 bit-rate: 36 Mbit/s power: 1. 85 W (0. 05 J/bit) latency: 10 s area: 15 mm 2 © 2001

Crisis in current (RT) design flow Problems Full spec Explore RTL Logic synthesis Ok? 68 COST E F F O R T © 2001

Objectives • Drastically shorten design time (months to weeks!) raise the abstraction level • Meet timing constraints as soon as possible expose timing bottlenecks at higher level • Low implementation cost systematic methodology to control cost 69 © 2001

(Re)Using High-Level Synthesis 70 U AC AC AC U U Conventional HLS ADOPT+HLS Less muxes/registers using ACUs (NOT conventional High-Level Synthesis) © 2001

Disabling the time-bomb for logic synthesis Synthesis time (minutes) 160 120 80 HLS 40 0 71 ADOPT + HLS Scheduling Logic synthesis © 2001

Exploration@High-level avoids complexity explosion (V)HDL lines (x 103) 8 6 4 2 HLS ADOPT + HLS 0 Behavior 72 RT Gate © 2001

Efficient use of high-level synthesis (I): reduced cost Gates (x 103) After logic synthesis ! 7 6 5 Muxes 4 Registers 3 Comb. logic 2 1 0 73 HLS ADOPT + HLS © 2001

Efficient use of high-level synthesis (II): improved delay Critical path HLS 74 After logic synthesis ! ADOPT+HLS © 2001

Results for programmable processors: cavity detection Performance (seconds) 16 14 12 10 8 6 4 2 0 75 a. CC +O 3 GCC -O 3 IMAGE: 1280 x 1000 pixels HP 9000/777 256 MB RAM +Adopt Initial +DTSE + Adopt (Glb. Trf. ) (Loc. Trf. ) © 2001

Analog-Digital Co-Design : FAST Demonstrator: 5 GHz WLAN terminal Mixed-signal front-end architecture exploration -> tools Analog/digital partitioning MCM vs. on-chip passives LNA ADC LO 76 Chip-package codesign -> architectures Chip partitioning Digital channel filtering Noise coupling in mixed-signal Ics -> tools & methods © 2001

The Desics pipeline Alcatel National Philips Ericsson Intel ESA D 6 RESEARCH PROGRAMME D 6/ INDUSTRY TRANSFER PROJECTS Industry product development 78 © 2001

Strategic Research Cooperation Wireless Local Area Network MPEG-4 System-on-Chip Design Technology 79 © 2001

IMEC is part of a closed loop ‘Closed Loop’ approach: Knowledge creation State-of-the-art science parks Venture capital Entrepreneurship Permanent training initiatives 80 You cannot make an economic engine running without a ‘closed belt’. Only the right combination of ALL elements can foster a successful industrial development, based upon an increasingly knowledge based society. © 2001

Conclusions - requirements for future embedded system applications learned from IIAP’s by: - building demonstrators - systematic design flows and methods - white box IP re-use - design automation - transfer through education & training http: //www. imec. be/ocapi http: //www. imec. be/3/3. 6. html 81 © 2001

Ivo Bolsens Vice President Paul Six Associate VP Niek Van Dierdonck DST DSP Technology Support Ivo Bolsens Vice President Jan Bormans Francky Catthoor Didi Verkest MICS SEMP EMSYS Multi-media System Exloration for Embedded Systems Image Compression Memory and Power Systems 82 Hugo De Man Senior Fellow Jean Roggen Manager Strategic Programmes Annemie Stas Administration Marc Engels Department Director Stėphane Donnay Serge Vernalde Bert Gyselinckx MIRA DBATE WISE Mixed Signal and RF Digital Broadband Wireless Systems Applications Terminals © 2001