General Interconnection design PCI R Reg PCI W

General Interconnection design PCI R Reg PCI W Reg PCI R/W Reg MB R Reg MB W Reg LAD[31: 0] Mux 32 MB R/W Reg PCI R /MB R Reg MBD[127: 0] PCI R /MB W Reg PCI R /MB R/W Reg PCI W /MB R Reg PCI W /MB W Reg Mux PCI W /MB R/W Reg Mux PCI R/W /MB R Reg PCI R/W /MB W Reg Mux PCI R/W /MB R/W Reg Mux 128

10 I/O Control Register 16 PCI Translation Base 16 MBus Upper Memory Address 16 MBus Lower Memory Address 16 MBus Translation Base 16 MBus Error Register Data Busses 32 PIO PCI to MB register 128 LAD[31: 0] 32 128 PIO MB to PCI register Mux Broadcast Status Register 32 32 Crate Master Register 32 Internal Control Register Internal Request Register 32 MBD[127: 0] 32 Internal Test Register 8 User Output Register User Input Register 8 Geographic Address Register 32 32 Mapper Array 128 Data FIFO 32 10 Address FIFO 32 PCI In Address Register PCI Out Address Register 32 128

Memory Magic Bus Group I/O Control PIO Configuration PIO Transfers TSI Registers Mapper Registers Data storage Function Offset Type Width (bits) Local bus Depth (Words) accesses Base Address Width (bits) Depth (Words) accesses I/O Control Register 0 x 0000 Register None LBA 0 10 b 1 R/W PCI Translation Base 0 x 0010 Register None LBA 0 16 b 1 R/W MBus Upper Memory Address 0 x 0014 Register None LBA 0 16 b 1 R/W MBus Lower Memory Address 0 x 0018 Register None LBA 0 16 b 1 R/W MBus Translation Base 0 x 001 C Register None LBA 0 16 b 1 R/W MBus Error Register 0 x 0020 Register None LBA 0 16 b 1 R/W PIO PCI to MB register win A/B ? Register 128 b 1 R LBA 1/2 32 b 1 W PIO MB to PCI register ? Register 128 b 1 W LBA 1 32 b 1 R Broadcast Status Register 0 x 010 C Register None LBA 0 32 b 1 R Crate Master Register 0 x 0110 Register None LBA 0 32 b 1 R/W Scaler Register 0 x 0114 Register None LBA 0 32 b 1 R/W Internal Control Register 0 x 0130 Register None LBA 0 32 b 1 R/W Internal Request Register 0 x 0134 Register None LBA 0 32 b 1 R Internal Test Register 0 x 013 C Register None LBA 0 32 b 1 R/W User Output Register 0 x 0140 Register None LBA 0 8 b 1 R/W User Input Register 0 x 0144 Register None LBA 0 8 b 1 R Geographic Address Register 0 x 0148 Register None LBA 0 32 b 1 R Mapper Array 0 x 1000 RAM None LBA 0 32 b 0 x 400 R/W Data FIFO ? FIFO 128 b 0 x 1000 W LBA 0 32 b 0 x 4000 R Address FIFO ? FIFO 10 b 0 x 1000 W LBA 0 10 b 0 x 1000 R

10 I/O Control Register 16 PCI Translation Base 16 MBus Upper Memory Address 16 MBus Lower Memory Address 16 MBus Translation Base 16 MBus Error Register 32 PIO PCI to MB register LAD[31: 0] 128 Data Busses 32 128 PIO MB to PCI register Broadcast Status Register 32 32 32 Crate Master Register 32 Scaler Register 32 Internal Control Register Internal Request Register 32 32 Internal Test Register 8 User Output Register User Input Register 8 Geographic Address Register 32 32 Mapper Array 128 Data FIFO 32 10 Address FIFO 32 PCI In Address Register PCI Out Address Register 32 MBD[127: 0] 128

fifo_full fifo_empty dma_access ecl_access mb_access pci_access plx_access vme_activity mb_clk_in gmb_clk_in pci_clk_in gpci_clk_in n_vme_rst_out n_vme_rst_in n_sw_rst_off n_sw_rst_on n_led_reset n_ads ale n_bigend n_blast breqi breqo n_bterm n_den dmpaf_eot dp<3. . 0> n_dt_r lad<31. . 0> n_lbe<3. . 0> lholda n_lw_r n_lserr n_ready n_wait n_linto n_dack<1. . 0> n_dreq<1. . 0> n_ccs lclk n_linti n_lb_reset useri_llocki usero_llocko pmereq XCV 405 E DISPLAY CLOCK MAGIC BUS RESET TSI LOCAL BUS TEST POINTS mbd<127. . 0> mba<31. . 0> mod_done<18. . 0> ev_loaded<3. . 0> n_bossreq n_dstrobe n_bossin bossgrin n_bossout bossgrout n_ddonein doneout n_ddoneout n_rd_wr n_startload n_bufin 1 n_bufin 0 n_bufout 1 n_bufout 0 fifoemptyin n_fifoemptyout n_resetin n_resetout n_mbmaster n_crmaster n_mben n_mbdatdir n_mbadddir vbd_start_req vbddone l 2_answer_ready ext_tsi_int_req j 2_resv_out<7. . 0> j 2_resv_in<7. . 0> n_gap n_ga<4. . 0> test_out<3. . 0> tsi_out<31. . 0> test_pt<31. . 0>

fifo_full fifo_empty dma_access ecl_access mb_access pci_access plx_access vme_activity mb_clk_in gmb_clk_in pci_clk_in gpci_clk_in n_vme_rst_out n_vme_rst_in n_sw_rst_off n_sw_rst_on n_led_reset Rst & Display & Clock Display management XCV 405 E MAGIC BUS Address translator Clock management Address decoder Add mapper Reset management State machine Add translator n_ads ale n_bigend n_blast breqi breqo n_bterm n_den dmpaf_eot dp<3. . 0> n_dt_r lad<31. . 0> n_lbe<3. . 0> lholda n_lw_r n_lserr n_ready n_wait n_linto n_dack<1. . 0> n_dreq<1. . 0> n_ccs lclk n_linti n_lb_reset useri_llocki usero_llocko pmereq LOCAL BUS INTERFACE Address decoder PIO Block TSI Block PIO registers TSI registers State machine TEST POINTS mbd<127. . 0> mba<31. . 0> mod_done<18. . 0> ev_loaded<3. . 0> n_bossreq n_dstrobe n_bossin bossgrin n_bossout bossgrout n_ddonein doneout n_ddoneout n_rd_wr n_startload n_bufin 1 n_bufin 0 n_bufout 1 n_bufout 0 fifoemptyin n_fifoemptyout n_resetin n_resetout n_mbmaster n_crmaster n_mben n_mbdatdir n_mbadddir vbd_start_req vbddone l 2_answer_ready ext_tsi_int_req j 2_resv_out<7. . 0> j 2_resv_in<7. . 0> n_gap n_ga<4. . 0> test_out<3. . 0> tsi_out<31. . 0> test_pt<31. . 0>

LOCAL BUS INTERFACE 32 PCI In Address Register Address decoder pci_en_wr_mem_1 pci_ en_rd_mem_1 pci_ en_buf_mem_1 Combinatorial Logics pci_ en_buf_mem_n n_ads 32 ale PCI Out Address Register lad<31. . 0> data_in<31. . 0> State machine n_bigend n_blast breqi breqo n_bterm n_den dmpaf_eot dp<3. . 0> n_dt_r n_lbe<3. . 0> lholda n_lw_r n_lserr n_ready n_wait n_linto n_dack<1. . 0> n_dreq<1. . 0> n_ccs lclk n_linti n_lb_reset useri_llocki usero_llocko pmereq pci_add_in<31. . 0> data_out<31. . 0> pci_add_out<31. . 0> pci_ en_wr pci_ en_rd int_pci_mb int_mb_pci dma_pci_mb

MAGIC BUS INTERFACE Magic Bus In Address Register 32 32 Address decoder mb_en_wr_mem_1 mb_en_rd_mem_1 mb_en_buf_mem_1 Combinatorial Logics mb_en_buf_mem_n Magic Bus Out Address Register mba<31. . 0> mb_add_in<31. . 0> mb_add_out<31. . 0> State machine mb_en_wr mb_en_rd mod_done<18. . 0> ev_loaded<3. . 0> n_bossreq n_dstrobe n_bossin bossgrin n_bossout bossgrout n_ddonein doneout n_ddoneout n_rd_wr n_startload n_bufin 1 n_bufin 0 n_bufout 1 n_bufout 0 fifoemptyin n_fifoemptyout n_resetin n_resetout n_mbmaster n_crmaster n_mben n_mbdatdir n_mbadddir mbd<127. . 0> int_pci_mb int_mb_pci dma_pci_mb data_in<127. . 0> data_out<127. . 0>

PIO Block PIO registers 10 I/O Control Register State machine 16 PCI Translation Base 16 MBus Upper Memory Address data_in<127. . 0> pci_en_wr_io_ctrl_reg pci_en_rd_io_ctrl_reg pci_en_wr_pci_trans_base pci_en_rd_pci_trans_base pci_en_wr_mb_up_mem_add pci_en_rd_mb_up_mem_add pci_en_wr_mb_low_mem_base pci_en_rd_mb_low_mem_base pci_en_wr_mb_err_reg pci_en_rd_mb_err_reg pci_en_wr_pci_to_mb_reg pci_en_rd_pci_to_mb_reg mb_en_wr_pci_to_mb_reg mb_en_rd_pci_to_mb_reg pci_en_wr_mb_to_pci_reg pci_en_rd_mb_to_pci_reg mb_en_wr_mb_to_pci_reg mb_en_rd_mb_to_pci_reg data_out<127. . 0> 16 MBus Lower Memory Address 16 MBus Translation Base 16 MBus Error Register 32 PIO PCI to MB register 128 PIO MB to PCI register 128 32 Address Translator fifoemptyin mb_add_in<31. . 0> mb_add_out<31. . 0> pci_add_in<31. . 0> pci_add_out<31. . 0>