General Info Purpose Applications Interrupt Priority IVT Interrupts

• General Info • Purpose/ Applications • Interrupt Priority/ IVT Interrupts • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts Nurudeen Olayiwola Thomas Gutierrez • Example • Conclusion 1

• General Info • Purpose/ Applications • Interrupt Priority/ IVT Question? ? • When you are at home sitting on your lazy boy, how do you know when someone wants to talk to you on the phone? • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example – Do you periodically get up and pick up the phone to see if someone is there? – Or do you wait till the phone rings to answer it? • Conclusion 2

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts Answer? • The first scenario shows a person doing what is known as polling. • The second case illustrates an interrupt-driven person. • Non-maskable interrupts • Example • Conclusion 3

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Polling • AKA “busy waiting”; looping program • Continues checking status register until a particular state exists • “Are we there yet? ” • What happens if something occurs at other devices while the processor is busy waiting? ? 4

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Interrupt • Device sends a special signal to CPU when data arrives. • “Wake me up when we get there. ” • Responds to hardware interrupt signal by interrupting current processing. • Now CPU can perform tasks before and after interrupt instead of just polling!! Good! 5

General Interrupt Flow • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts 1. 2. 3. 4. 5. Completes current instruction Saves current state to status registers Identify source Jump to and activate Interrupt Service Routing (ISR) Return to original program (RTI) and restore state • Maskable interrupts • Non-maskable interrupts Register CPU Interrupt driven • Example • Conclusion I/O device 6

• General Info Interrupts: Flow Chart • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts SOFTWARE HARDWARE INTERRUPT STACK MPU REGISTER CONTENTS • Maskable interrupts • Non-maskable interrupts SET APPROPRIATE BIT IN CCR MASK SET? N Y CONTINUE MAIN PROGRAM $FFC 0 • Example • Conclusion EXECUTE INTERRUPT SERVICE ROUTINE LOAD INTERRUPT VECTOR INTO PROGRAM COUNTER VECTOR TABLE $FFFF 7

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Brief Background • Univac 1103/1103 A (1953 -56) – first recognized CPU with interrupts. Current instruction was stored in memory and program counter loaded with a fixed address. • Other notables: – IBM (1954) – first to use interrupt masking – NBS DYSEAC (1954) – first with I/O interrupts 8

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Purpose/Applications • To modify or do additional instructions based on internal requests and/or external devices. • Provide a means for suspending current instructions for more important tasks. • Hardware (called Interrupts or Resets) – Reset – User-defined interrupt – Timer operations – CPU operations monitor failure • Software – Illegal instruction – SWI 9

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Purpose/Applications (cont. ) • Coordinating I/O operations • Notifies the CPU that an input is ready or an output can be changed • Timing • Periodic (clock-driven) interrupts remind the CPU of the passage of time • Multi-tasking • Updating counters • Timing during interactive programs • Errors • Interrupts can notify of error situations 10

• General Info Purpose/Applications (cont. ) • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Practical uses/examples • Change direction of a motor. • Auto wiper speed increased or decreased. • Pressing a pause button on a VCR • HC 11 controlled transmission system • Etc. • Example • Conclusion 11

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Types of interrupts • Ignorable interrupts (or Maskable) – Most often used – Good for using when computer needs to do something more important – When the interrupt mask is set, interrupts are hidden and therefore are ignored. • Non-ignorable interrupts (Nonmaskable) • NMI’s take precedence and interrupt any task 12

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Interrupt Vector Table • When an interrupt occurs, control of the program moves to the interrupt handling routine – Event similar to subroutine – How do we know where the handler routine is though? ? • The address of the handler is provided by the interrupt vector table – IVT has one entry for each type of interrupt – Each entry is indexed by interrupt type, and includes a pointer to the handler 13

Interrupt Vector Table Maskable when the Ibit of CCR is set • General Info • Purpose/ Applications lowest priority • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example highest priority • Conclusion 14 Unmaskable

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts Maskable/Unmaskable • 6 Non-Maskable – always interrupt the program execution • 15 Maskable – can enable or disable by mask bits – HOW? • Example • Conclusion 15

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts Stacking order When an interrupt occurs: 1. Finish execution of the current instruction Note: Non-maskable interrupts and resets happen immediately SP-8 CCR SP-7 ACCB SP-6 ACCA 2. HC 11 pushes on stack: PC, accumulators and registers, CCR SP-5 IXH SP-4 IXL SP-3 IYH SP-2 IYL SP-1 PCH SP-0 PCL 3. HC 11 sets the I-bit Masks interrupts - can’t interrupt an interrupt 4. Looks up vector of highest-priority interrupt • Non-maskable interrupts 5. Branches to interrupt service routine Executes until RTI is encountered • Example 6. Restores accumulators and registers, CCR from stack (note: this includes restoring the I-bit of CCR) • Conclusion SP-9 7. Returns to instruction after the one that was interrupted (note: other interrupts may be pending now) 16

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example Controlling Interrupts: The I-bit • Exists as bit 4 in the Condition Code Register (CCR) – When set (I=1), interrupts will be inhibited and placed as pending – When cleared (I=0), interrupt servicing will be allowed when asked • The I bit is always set while servicing an interrupt; Interrupts can’t nest • Set during RESET to allow minimum system initialization • Conclusion 17

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example Controlling Interrupts: The I-bit • Can also be set by software to prevent execution of maskable interrupts – SEI (SEt Interrupt Mask) • Can be cleared by software instructions – CLI (CLear Interrupt Mask) • Automatically cleared by RTI instruction • Conclusion 18

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example Maskable Interrupt: HPRIO • Can elevate the priority of one of the maskable interrupts. • Uses bits 0 -3 of HPRIO (Highest PRIOrity Interrupt Register) • Default is IRQ. • Can be set at anytime during program as long as I bit is set. • Conclusion 19

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Maskable Interrupt: IRQ • Highest priority maskable interrupt • IRQ pin provides additional external interrupting source • Other additional MCU pins can be used as interrupt inputs: – Example: • XIRQ input • Main-Timer Capture Pins • Pulse Accumulator Pin • IRQE Bit in the OPTION control used to specify IRQ pin configuration – IRQE = 0 -> Low level sensitive – IRQE = 1 -> Low-going edge sensitive (single source only) 20

Maskable Interrupt: IRQ • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Controlled by a pin on the HC 11 • A low signal will initiate interrupt sequence • Maskable interrupts • Non-maskable interrupts • Example 0 • Conclusion 1 21

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example Non-maskable Interrupt: XIRQ • Enabled by TAP instruction by clearing X-bit upon system initialization • After being cleared, software cannot set the X-bit, thus XIRQ is non-maskable. • Higher priority than any source maskable by the I-bit. • Both the X and I bits are automatically set by hardware after stacking the CCR. • RTI restores X and I bit to pre-interrupt states • Conclusion 22

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts Non-maskable Interrupt: SWI • Software instruction, thus cannot be interrupted until completed • Uninhibited by global mask bits in the CCR • Similar to other interrupts, sets the Ibit upon servicing • Example • Conclusion 23

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts Example - IRQ handler 1. Write the IRQ handler routine IRQHANDLE ORG $3000 ldaa count inca staa count ldx #msg jsr OUTSTRG ldx #count jsr OUT 1 BYT rti org $2000 ; A <-- current count ; increment count ; write back count ; print out msg ; print out count ; all done – return ; data section 2. Write the initialization and main routine msg fcc “Number of times button pressed: ” fcb $04 count fcb org JMP 0 ; button counter $00 ee IRQ vector IRQHANDLE at $FFF 2 • Example • Conclusion >>Whenever button is pushed, update a counter and print out the current count 3. Do-nothing program! loop org cli bra $2200 loop ; main program ; enable interrupts ; endless loop 24

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example The SIX untouchables: • • • NONMASKABLE RESET CLOCK MONITOR COP Watchdog Illegal Opcode XIRQ SWI • Conclusion 25

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Advantages and Disadvantages • Advantage 1. Efficient, better than polling 2. Multitasking • Disadvantage 1. They can occur randomly 2. Requires additional hardware, sometimes 26

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts Questions? ? • Non-maskable interrupts • Example • Conclusion 27

• General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts References http: //courses. cs. tamu. edu/cpsc 462/ walker/Slides/Exceptions_Interrupts_1. ppt http: //oa-003. spu. edu/bolding/ee 3280/nosound/16 Exceptions. ppt Previous semester presentations… • Non-maskable interrupts • Example • Conclusion 28