GBT slow control architecture proposal EPESEBE General overview

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GBT slow control architecture proposal EP-ESE-BE

GBT slow control architecture proposal EP-ESE-BE

General overview q. Common use § 2 bits dedicated to the internal control of

General overview q. Common use § 2 bits dedicated to the internal control of the GBTx § 1 SCA per GBT Link (2 dedicated bits) IC EC Slow control Back-end FPGA GBTFPGA (GBTx + SCA) GBTFPGA (GBTx + SCA) FE FE FE

General overview q. HDLC: § Protocol used to communicate with the SCA § Generic

General overview q. HDLC: § Protocol used to communicate with the SCA § Generic data field contains specific information: o o o ID: Transaction ID – Used to link the reply with the command CH: Interface – (internal register, I 2 C, GPIO …) LEN: Length of the DATA field CMD: Command specific to the channel selected (set GPIO, read GPIO…) ERR: Error field (busy, CRC error…)

Architecture overview q. GBT-SC module § § Implemented outside of the GBT-BANK Manage the

Architecture overview q. GBT-SC module § § Implemented outside of the GBT-BANK Manage the 4 slow controls bits (Internal Control and External Control) + additional SCA managed by e-links Configured by a memory mapped bus (device agnostic – bridge to Avalon-MM and AXI will be include in ref. design) Broadcast supported FPGA Memory Mapped bus Data Link 0 [83: 0] Data Link 1 [83: 0] GBTSC-IP Data Link n [83: 0] … GBT-BANK

Architecture overview q. GBT-SC module: § Manage 2 bits for the Internal Control (IC)

Architecture overview q. GBT-SC module: § Manage 2 bits for the Internal Control (IC) § Manage 2 bits for the External Control (EC) § Could manage additional SCA that used “user” e-links (e. g. : e-links k 2, k 5, k 35 and k 38 are connected to SCAs) GBT-SC Memory Mapped bus Command 2 bit generation Config. package Placement (mask) Data[83: 0] IC 1. . 0 Elin k 39 Bits 1. . 0 Elin k 38 Bits 1. . 0 Elin k 37 Bits 1. . 0 Elin k 36 Bits 1. . 0 Elin k 35 Bits 1. . 0 Elin k 34 Bits 1. . 0 Elin k 33 Bits 1. . 0 Elink 32 Bits 1. . 0 80 Mb/s Elin k 7 Bits 1. . 0 Elin k 6 Bits 1. . 0 Elin k 5 Bits 1. . 0 Elin k 4 Bits 1. . 0 Elin k 3 Bits 1. . 0 Elin k 2 Bits 1. . 0 Elin k 1 Bits 1. . 0 Elink 0 Bits 1. . 0 FEC 31. . 0

q SCA access § Write (32 bit data): o 2 GBTSC-IP registers to be

q SCA access § Write (32 bit data): o 2 GBTSC-IP registers to be written o 112 bits @ 80 Mbit/s (SOF, Addr…) § Read (32 bit data): o 1 write transaction o Cable latency (wait for reply) o 112 bits @ 80 Mbit/s o 1 GBTSC-IP register to be written / SCA (selection) o 1 GBTSC-IP register to be read / SCA (data) q 128 bit to 1 SCA § 9 SCA write accesses o 18 register access o 2016 bits @ 80 Mbit/s § 4 SCA read accesses o 16 register access o 896 bits @ 80 Mbit/s o 4 response time § § § 34 GBTSC-IP registers accesses (R/W) 2912 bits @ 80 Mbit/s 4 x the response time of the SCA Start Enable JTAG Get TDO[1] Set FREQ Get TDO[2] Set TDI[0] Get TDO[3] Set TDI[1] End ? Set TDI[2] Set TDI[3] Set TMS[0] Set TMS[1] Set TMS[2] Send without reply checking Critical case: JTAG End Set TMS[3] JTAG GO Busy? Check replies Get TDO[0]

Critical case: JTAG (Programming an Artix 7) q Uncompressed: 2 MBytes (16 777 216

Critical case: JTAG (Programming an Artix 7) q Uncompressed: 2 MBytes (16 777 216 bits -> 131 072 * 128 bits): § § § 4 456 448 GBTSC-IP transactions (R/W) 381 664 bits @ 80 Mbit/s 524 288 x the latency [ignored because unknown] o GBT-FPGA latency optimized: Tx/Rx = 5 clock cycle @ 240 Mhz (Arria 10) = 21 ns o Cable: 3, 335640952 µs/km -> for 100 m = 333 ns q E. g: using TCP/IP @ 100 Mbit/s § 1 transaction (992 bits): o o o Ethernet header: 112 bits IP header: 192 bits TCP header: 160 bits Data (register addr. and data): 64 bits Latency (because of the ACK) [ignored because unknown] ACK (Ethernet header + IP header + TCP header) § Total time: o o 381 664 bits @ 80 Mbit/s = 4. 55 s GBT latency: 524 288 x 350 = 0. 190 s 4 216 Mbits @ 100 Mbit/s = 42. 16 s [bottleneck] 4 456 448 Ethernet latency = unknown [bottleneck? ] Bottleneck: PC to FPGA transaction GBTSC-IP control moved to the FPGA?

Critical case: JTAG q. Bit file written into TDI/TMS FIFOs § Allow burst mode

Critical case: JTAG q. Bit file written into TDI/TMS FIFOs § Allow burst mode q. JTAG FSM § Manage GBTSC-IP § Read TDI/TMS FIFOs § Write TDO FIFO Memory Mapped bus FIFO (TDI) Memory Mapped bus FIFO (TMS) Memory Mapped bus FIFO (TDO) GBT-BANK JTAG FSM GBTSC-IP GBT-BANK

Status q. Architecture design (on-going) q. HDL design to start mid-November § Divided in

Status q. Architecture design (on-going) q. HDL design to start mid-November § Divided in 2 parts o First delivery (GBTSC-IP): Feb. 2017 o Second delivery (JTAG FSM): mid 2017 § Device agnostic § Testbench? (discussion with Ph. D. From CBM)

Register map q Enable SCA: § 1 bit per SCA -> Allow broadcast §

Register map q Enable SCA: § 1 bit per SCA -> Allow broadcast § X register of 32 bits (depends on the number of SCA) Enable SCA 0 to 31 q Id – Ch – Len – Cmd and Data Enable SCA (n-32) to n 0 x 00 + (n/32) Id - Ch - Len - Cmd 0 x 01 + (n/32) Data 0 x 02 + (n/32) Control / Status 0 x 03 + (n/32) Rd only Err. flags SCA 0 to 31 0 x 04 + (n/32) Rd only Err. flags SCA (n-32) to n 0 x 04 + 2*(n/32) SCA sel. 0 x 05 + 2*(n/32) Rd only Id - Ch - Len - Err 0 x 06 + 2*(n/32) Rd only Data 0 x 07 + 2*(n/32) § Used to construct the HDLC frame § Transmission automatically start when data is written q Control/Status § § Transmission done flag Reply received flag General error flag (ORing of all error flags) Watchdog for reply (config) q Err. Flag § 1 bit per SCA q SCA sel. § Select reply to be read q Id – Ch – Len – Err and Data § Reply of selected SCA 0 x 00 * n: number of SCAs

GBT-SC bloc diagram Memory Mapped bus Configuration package Data … Data Config Enable SCA

GBT-SC bloc diagram Memory Mapped bus Configuration package Data … Data Config Enable SCA 0 to 31 Enable SCA (n-32) to n Id - Ch - Len - Cmd Data HDLC encoder Mux. TX Demux. RX Serializer Control / Status Err. flags SCA 0 to 31 Err. flags SCA (n-32) to n Err. detect HDLC decoder Deser ializer Link sel. Id - Ch - Len - Err Data Rd. … FIFO x. N (multiple instantiation)

BASIC GBTSC + ACCEL MODULES MASTER PCIe / TCP-IP / JTAG GBT-FPGA RAM Protocol

BASIC GBTSC + ACCEL MODULES MASTER PCIe / TCP-IP / JTAG GBT-FPGA RAM Protocol Mux GBTSC-IP

Configuration Package SCA# GBT# Bits# 1 1 EC[1. . 0] 2 1 D[15. .

Configuration Package SCA# GBT# Bits# 1 1 EC[1. . 0] 2 1 D[15. . 14] 3 2 EC[1. . 0] . . . N M EC[1. . 0]