FSMs and Synchronization Asynchronous Inputs in Sequential Systems

Handling Metastability § Preventing metastability turns out to be an impossible problem § High

Handling Metastability How many registers are necessary? § Depends on many design parameters(clock speed,

Finite State Machines § Finite State Machines (FSMs) are a useful abstraction for sequential

Two Types of FSMs § Moore FSMs 輸出只與目前狀態有關 § Mealy FSMs 輸出與目前狀態及輸入有關 § Moore

Moore FSMs § Moore and Mealy FSMs are distinguished by their output generation

FSM Design Example : Level-to-Pulse § 功能：A level-to-pulse converter produces a single-cycle pulse each

State Transition Diagrams § 如何設計Level to Pulse FSM? 狀態轉移圖是一種非常有用之具。

Logic Derivation for a Moore FSM § 對應之組合邏輯應用K -map化簡

Moore/Mealy Trade-Offs Remember that the difference is in the output: • Moore outputs are

Verilog for the Moore Vender module moore. Vender (N, D, Q, DC, DN, DD,

parameter IDLE = 0; parameter GOT_5 c = 1; parameter GOT_10 c = 2;

always @ (posedge clk or negedge reset) if (!reset) state <= IDLE; else state

always @ (state or N or D or Q) begin case (state) IDLE: if

assign DC = (state == GOT_30 c || state == GOT_35 c || state

Coding Alternative: Two Blocks always @ (state or N or D or Q) begin

FSM Output Glitching § FSM state bits may not transition at precisely the same

§ If the soda dispenser is glitch-sensitive, your customers can get a 20 -cent

Registered FSM Outputs are Glitch-Free reg DC, DN, DD; // Sequential always block for

Verilog for Mealy FS module mealy. Vender (N, D, Q, DC, DN, DD, clk,

always @ (state or N or D or Q) begin DC = 0; DN

Summary § Synchronize all asynchronous inputs § Use two back to back registers §

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FSMs and Synchronization

Asynchronous Inputs in Sequential Systems

Handling Metastability § Preventing metastability turns out to be an impossible problem § High gain of digital devices makes it likely that metastable conditions will resolve themselves quickly § Solution to metastability: allow time for signals to stabilize

Handling Metastability How many registers are necessary? § Depends on many design parameters(clock speed, device speeds, …), one or maybe two synchronization registers is sufficient

Finite State Machines § Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized “states” of operation § At each clock edge, combinational logic computes outputs and next state as a function of inputs and present state

Finite State Machines

Two Types of FSMs § Moore FSMs 輸出只與目前狀態有關 § Mealy FSMs 輸出與目前狀態及輸入有關 § Moore and Mealy FSMs are distinguished by their output generation

Moore FSMs § Moore and Mealy FSMs are distinguished by their output generation

Mealy FSMs

FSM Design Example : Level-to-Pulse § 功能：A level-to-pulse converter produces a single-cycle pulse each time its input goes high. In other words, it’s a synchronous rising edge detector. § 應用例: Buttons and switches pressed by humans for arbitrary periods of time Singlecycle enable signals for counters

FSM Design Example : Level-to-Pulse

State Transition Diagrams § 如何設計Level to Pulse FSM? 狀態轉移圖是一種非常有用之具。

State Transition Diagrams

Logic Derivation for a Moore FSM § 對應之組合邏輯應用K -map化簡

Moore Level-to-Pulse Converter

Design of a Mealy Level-to. Pulse

Mealy Level-to-Pulse Converter

Moore/Mealy Trade-Offs Remember that the difference is in the output: • Moore outputs are based on state only • Mealy outputs are based on state and input • Therefore, Mealy outputs generally occur one cycle earlier than a Moore: Compared to a Moore FSM, a Mealy FSM might. . . • Be more difficult to conceptualize and design • Have fewer states

FSM Timing Requirements

Vending Machine

What States are in the System?

A Moore Vender

State Reduction

Verilog for the Moore Vender module moore. Vender (N, D, Q, DC, DN, DD, clk, reset, state); input N, D, Q, clk, reset; output DC, DN, DD; output [3: 0] state; reg [3: 0] state, next;

parameter IDLE = 0; parameter GOT_5 c = 1; parameter GOT_10 c = 2; parameter GOT_15 c = 3; parameter GOT_20 c = 4; parameter GOT_25 c = 5; parameter GOT_30 c = 6; parameter GOT_35 c = 7; parameter GOT_40 c = 8; parameter GOT_45 c = 9; parameter GOT_50 c = 10; parameter RETURN_20 c = 11; parameter RETURN_15 c = 12; parameter RETURN_10 c = 13; parameter RETURN_5 c = 14

always @ (posedge clk or negedge reset) if (!reset) state <= IDLE; else state <= next;

always @ (state or N or D or Q) begin case (state) IDLE: if (Q) next = GOT_25 c; else if (D) next = GOT_10 c; else if (N) next = GOT_5 c; else next = IDLE; GOT_5 c: if (Q) next = GOT_30 c; else if (D) next = GOT_15 c; else if (N) next = GOT_10 c; else next = GOT_5 c; GOT_10 c: if (Q) next = GOT_35 c; else if (D) next = GOT_20 c; else if (N) next = GOT_15 c; else next = GOT_10 c; GOT_15 c: if (Q) next = GOT_40 c; else if (D) next = GOT_25 c; else if (N) next = GOT_20 c; else next = GOT_15 c; GOT_20 c: if (Q) next = GOT_45 c; else if (D) next = GOT_30 c; else if (N) next = GOT_25 c; else next = GOT_20 c; GOT_25 c: if (Q) next = GOT_50 c; else if (D) next = GOT_35 c; else if (N) next = GOT_30 c; else next = GOT_25 c; GOT_30 c: next = IDLE; GOT_35 c: next = RETURN_5 c; GOT_40 c: next = RETURN_10 c; GOT_45 c: next = RETURN_15 c; GOT_50 c: next = RETURN_20 c; RETURN_20 c: next = RETURN_10 c; RETURN_15 c: next = RETURN_5 c; RETURN_10 c: next = IDLE; RETURN_5 c: next = IDLE; default: next = IDLE; endcase end

assign DC = (state == GOT_30 c || state == GOT_35 c || state == GOT_40 c || state == GOT_45 c || state == GOT_50 c); assign DN = (state == RETURN_5 c); assign DD = (state == RETURN_20 c || state == RETURN_15 c || state == RETURN_10 c); endmodule

Simulation of Moore Vender

Coding Alternative: Two Blocks always @ (state or N or D or Q) begin DC = 0; DD = 0; DN = 0; // defaults case (state) IDLE: if (Q) next = GOT_25 c; else if (D) next = GOT_10 c; else if (N) next = GOT_5 c; else next = IDLE; GOT_5 c: if (Q) next = GOT_30 c; else if (D) next = GOT_15 c; else if (N) next = GOT_10 c; else next = GOT_5 c; GOT_10 c: if (Q) next = GOT_35 c; else if (D) next = GOT_20 c; else if (N) next = GOT_15 c; else next = GOT_10 c; GOT_30 c: begin DC = 1; next = IDLE; end GOT_35 c: begin DC = 1; next = RETURN_5 c; end GOT_40 c: begin DC = 1; next = RETURN_10 c; end GOT_45 c: begin DC = 1; next = RETURN_15 c; end GOT_50 c: begin DC = 1; next = RETURN_20 c; end RETURN_20 c: begin DD = 1; next = RETURN_10 c; end GOT_15 c: if (Q) next = GOT_40 c; else if (D) next = GOT_25 c; else if (N) next = GOT_20 c; else next = GOT_15 c; GOT_20 c: if (Q) next = GOT_45 c; else if (D) next = GOT_30 c; else if (N) next = GOT_25 c; else next = GOT_20 c; RETURN_15 c: begin DD = 1; next = RETURN_5 c; end RETURN_10 c: begin DD = 1; next = IDLE; end RETURN_5 c: begin DN = 1; next = IDLE; end GOT_25 c: if (Q) next = GOT_50 c; else if (D) next = GOT_35 c; else if (N) next = GOT_30 c; else next = GOT_25 c; default: next = IDLE; endcase end

FSM Output Glitching § FSM state bits may not transition at precisely the same time § Combinational logic for outputs may contain hazards § Result: your FSM outputs may glitch!

§ If the soda dispenser is glitch-sensitive, your customers can get a 20 -cent soda!

Registered FSM Outputs are Glitch-Free reg DC, DN, DD; // Sequential always block for state assignment always @ (posedge clk or negedge reset) begin if (!reset) state <= IDLE; else if (clk) state <= next; DC <= (next == GOT_30 c || next == GOT_35 c ||next == GOT_40 c || next == GOT_45 c ||next == GOT_50 c); DN <= (next == RETURN_5 c); DD <= (next == RETURN_20 c || next == RETURN_15 c ||next == RETURN_10 c); END

Mealy Vender (covered in Recitation)

Verilog for Mealy FS module mealy. Vender (N, D, Q, DC, DN, DD, clk, reset, state); input N, D, Q, clk, reset; output DC, DN, DD; reg DC, DN, DD; output [3: 0] state; reg [3: 0] state, next; parameter IDLE = 0; parameter GOT_5 c = 1; parameter GOT_10 c = 2; parameter GOT_15 c = 3; parameter GOT_20 c = 4; parameter GOT_25 c = 5; parameter RETURN_20 c = 6; parameter RETURN_15 c = 7; parameter RETURN_10 c = 8; parameter RETURN_5 c = 9; // Sequential always block for state assignment always @ (posedge clk or negedge reset) if (!reset) state <= IDLE; else state <= next;

always @ (state or N or D or Q) begin DC = 0; DN = 0; DD = 0; // defaults case (state) IDLE: if (Q) next = GOT_25 c; else if (D) next = GOT_10 c; else if (N) next = GOT_5 c; else next = IDLE; GOT_5 c: if (Q) begin DC = 1; next = IDLE; end else if (D) next = GOT_15 c; else if (N) next = GOT_10 c; else next = GOT_5 c; GOT_10 c: if (Q) begin GOT_25 c: if (Q) begin DC = 1; next = RETURN_20 c; end else if (D) begin DC = 1; next = RETURN_5 c; end else if (N) begin DC = 1; next = IDLE; end else next = GOT_25 c; RETURN_20 c: begin DC = 1; next = RETURN_5 c; end else if (D) next = GOT_20 c; else if (N) next = GOT_15 c; else next = GOT_10 c; DD = 1; next = RETURN_10 c; DC = 1; next = RETURN_10 c; end else if (D) next = GOT_25 c; else if (N) next = GOT_20 c; else next = GOT_15 c; RETURN_10 c: begin GOT_15 c: if (Q) begin GOT_20 c: if (Q) begin DC = 1; next = RETURN_15 c; end else if (D) begin DC = 1; next = IDLE; end else if (N) next = GOT_25 c; else next = GOT_20 c; end RETURN_15 c: begin DD = 1; next = RETURN_5 c; end DD = 1; next = IDLE; end RETURN_5 c: begin DN = 1; next = IDLE; end default: next = IDLE; endcase endmodule

Simulation of Mealy Vender

Summary § Synchronize all asynchronous inputs § Use two back to back registers § Two types of Finite State Machines introduced § Moore – Outputs are a function of current state § Mealy – outputs a function of current state and input § A standard template can be used for coding FSMs § Register outputs of combinational logic for critical control signals