# FSMbased Specification Formalisms Giovanni De Micheli Integrated Systems

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FSM-based Specification Formalisms Giovanni De Micheli Integrated Systems Laboratory This presentation can be used for non-commercial purposes as long as this note and the copyright footers are not removed © Giovanni De Micheli – All rights reserved

Module 1 u Objectives: s Finite-state machines s Synchronous languages s State Charts (c) Giovanni De Micheli 2

Models of computation u Data-flow oriented models s Focus on computation s Data-flow graphs and derivatives u Control-flow oriented models s Focus on control s Based on finite-state machine models u DF and CF model complementary aspects (c) Giovanni De Micheli 3

Formal FSM model u A set of primary inputs patterns X u A set of primary outputs patterns Y u A set of states S u A state transition function: s δ: X × S → S u An output function: s λ : X × S → Y for Mealy models s λ: S→Y for Moore models (c) Giovanni De Micheli 4

Finite-state machines Primary Inputs COMBINATIONAL CIRCUIT Primary Outputs REGISTERS clock u A finite-state machine is an abstraction u Computation takes no time s Outputs are available as soon as inputs are u A finite-state machine implementation is a sequential circuit with a finite cycle-time (c) Giovanni De Micheli 5

State diagrams u Directed graph s Vertices = states s Edges = transitions u Equivalent to state transition tables (c) Giovanni De Micheli 6

Example a’b’ + r/0 ab’r’/0 s 0 r/0 a’br’/0 a’r’/0 b’r’/0 s 1 abr’/1 r/0 br’/1 s 2 ar’/1 s 3 r’/1 (c) Giovanni De Micheli 7

FSM-based models u Synchronous languages: s Esterel, Argos, Lustre, SDL u Graphical formalisms: s FSMs, hierarchical FSMs, concurrent FSMs s State. Charts s Program-state machines s Spec. Charts (c) Giovanni De Micheli 8

State Charts u Proposed by Harel u Graphic formalism to specify FSMs with: s Hierarchy s Concurrency s Communication u Tools for simulation, animation and synthesis (c) Giovanni De Micheli 9

State Charts u States u Transitions u Hierarchy s OR (sequential) decomposition t s State → a sequence of states AND (concurrent) decomposition t State → a set of concurrent states (c) Giovanni De Micheli 10

State charts Top_level_uart transmitter receiver tx_mode rx_mode csr(2)=1 idle csr(3)=1 transmit idle receive csr(2)=0 csr(3)=0 load_thr / load: =1; tx_hold_reg; =data_in; empty loaded empty rd(tx_hold_reg)/load: =0 uart_mode [read_enable=1] / filoful: =1 loaded read_fifo_cmd/filoful: =0 [csr(2. . 3)=’ 11’] normal_tx_rx echo_active [csr(2. . 3)=’ 11’] (c) Giovanni De Micheli 11

State Charts Additional features u State transitions across multiple levels u Timeouts: s Notation on transition arcs denoting the max/min time in a given state u Communication: s Broadcast mechanism based on event generation and reception u History feature: s Keep track of visited states (c) Giovanni De Micheli 12

State. Charts u Advantages: s Formal basis s Easy to learn s Support of hierarchy, concurrency and exceptions t Avoid exponential blow up of states u Disadvantages: s No description of data-flow computation (c) Giovanni De Micheli 13

Program State Machines u Combining FSM formalism with program execution u In each state a specific program is active u Hierarchy: s Sequential states s Concurrent states u In a hierarchical state, several programs may be active (c) Giovanni De Micheli 14

Spec. Charts u Based on Program State Machines s Introduced by Gajski et al. u Extension of VHDL: s Compilable into VHDL for simulation and synthesis s Behavioral hierarchy u Combining FSM and VHDL formalisms s Leaves of the hierarchy are VHDL models (c) Giovanni De Micheli 15

Example E port P, Q: in integer; type int_array is array(natural range<>) of integer; signal A: int_array( 15 downto 0 ); B X Y x 1 variable i, max: integer; max-0; Z z 1 for i=1 to 20 do e 1 x 2 if (A[i] > max) then e 4 max = A[i]; z 2 end if; e 2 end for e 3 e 5 u TOC: e 2, e 3 u TI: e 1 (c) Giovanni De Micheli 16

State transitions u Sequencing between sub-behaviors are controlled by transition arcs s TOC - Transition on completion t s Program terminates AND transition condition is true TI - Transition immediate t Transition condition is true u A transition arc is labeled by a triple: s (transition type, triggering event, next behavior) (c) Giovanni De Micheli 17

Spec. Charts semantics u Timing semantics similar to VHDL u Synchronization: s Use wait statement s Use TOC looping back to the top of the program u Communication: s Using variables and signals s Message passing (send/receive) (c) Giovanni De Micheli 18

Module 2 u Objectives: s Expression-based formalisms s Control-flow expressions (c) Giovanni De Micheli 20

Expression-based formalisms u Represent sequential behavior by expressions u Advantages: s Symbolic manipulation s Translation into FSM models u Disadvantages: s Loss of data-flow information (c) Giovanni De Micheli 21

Control-flow expression formalism u Expressions capturing a high-level view of control-flow while abstracting data-flow information u Expressions are extracted directly from HDL or programming language specifications u Cycle-based semantics provides a formal interpretation of HDLs u Based on the algebra of synchronous processes (Process Algebra) (c) Giovanni De Micheli 23

Control-Flow Expressions Composition HDL CFE Sequential begin P; Q end p·q Parallel fork P; Q join p װ q if (c) Alternative P; else c: p+c: q Q; while (c) Loop P; wait (!c) P; Infinite (c) Giovanni De Micheli always P; (c: p)* (c: 0)*. p pω 24

Example of design problem Ethernet controller Receive Unit DMA-RCVD RXE Host CPU DMA-FRAME DMA-BUFFER DMA-BIT DMA-XMIT-FRAME XMIT-BIT RXD TXE Transmit Unit Memory CRS ENQUEUE EXEC-UNIT CDT Execute Unit System Bus Network Coprocessor u Problem s Avoid bus conflicts (c) Giovanni De Micheli 25

Example of design problem Ethernet controller MEMORY P 1 P 2 P 3 always begin write bus initialize wait ( free bus ) receive data wait ( tr ready ) read bus end end p = p 1 װ p 2 װ p 3 p 1 = [a. 0]ω p 2 = [0. (c: 0)*. a]ω p 3 = [(x: 0)*. a]ω (c) Giovanni De Micheli 26

Example Control-Flow Expressions MEMORY P 2 P 3 always begin P 1 write bus initialize wait ( free bus ) receive data wait ( tr ready ) read bus end end p = p 1 װ p 2 װ p 3 p 1 = [a. 0]ω p 2 = [0. (c: 0)*. a]ω p 3 = [(x: 0)*. a]ω NEVER = {a, a} u Never access the bus twice simultaneously (c) Giovanni De Micheli 29

Example Synchronization SENDER RECEIVER r k a a u Synchronization between a sender and a receiver in a blocking protocol s s Sender = (x : r)*. a Receiver = (y : k)*. a ALWAYS = {{a; a}} NEVER = {{r; k}} (c) Giovanni De Micheli 30

Design with CFEs u Representation: s A CFE can be compiled into a specification automaton s Representing all feasible behaviors u Synthesis: s A control-unit implementation is a FSM s Derivable from a specification automaton by assigning values to decision variables over time u Optimization: s Minimize a cost function defined over the decision variables (c) Giovanni De Micheli 31

CFE Summary u Control-flow expression are a modeling tool u Formal semantic: s Support for synthesis and verification u Synthesis path from CFEs to control-unit (c) Giovanni De Micheli 32

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