Front End Electronics for the NOv A Neutrino

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Front End Electronics for the NOv. A Neutrino Detector John Oliver, Nathan Felt Harvard

Front End Electronics for the NOv. A Neutrino Detector John Oliver, Nathan Felt Harvard University • Long baseline neutrino experiment • Fermilab (Chicago) to northern Minnesota (~800 km) • 20 - 25 k. Ton “Far” and smaller “Near” detectors 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 1

NOv. A Far Detector • ~ 640, 000 channels of liquid scintillator / wavelength

NOv. A Far Detector • ~ 640, 000 channels of liquid scintillator / wavelength shifting fiber cells • Readout by 32 channel Avalanche Photo Diodes (10 pf per pixel ) • Gain ~ 100 @ -15 C • MIP = ~ 25 photoelectrons @ far end of cell 2, 500 e / minimum ionizing signal • Neutrino interactions only in 10 ms spill every ~ 2 sec • Signal dominated by cosmic rays ~ 400 Hz/pixel 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 2

Readout Electronics & Noise APD noise • Minimum noise dominated by APD leakage of

Readout Electronics & Noise APD noise • Minimum noise dominated by APD leakage of ~ 1 – 2 n. A @ -15 C • Dual Correlated Sampling would yield current (parallel) noise of ~100 e rms @ DT ~ 1 ms Front end electronics & noise • Integrate signals in ASIC preamplifier with low noise density of ~ 1 – 2 n. V/rt(Hz) • Dual Correlated Sampling with controlled risetime constant of a few hundred ns would yield ~ 150 e rms Readout objective is to minimize both noise components Readout strategy • Sample & digitize each APD integrated signal continuously every 500 ns • Perform multiple correlated sampling filters in local FPGA • Extract pulseheight & timestamp locally for each hit • Find “in spill” hits by timestamp in DAQ system (no trigger or spill signals on Front End Board) 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 3

Front End Board (FEB) Architecture APD Module ASIC ADC DAQ FPGA TE Cooler Control

Front End Board (FEB) Architecture APD Module ASIC ADC DAQ FPGA TE Cooler Control • Thermoelectric cooler maintains – 15 C at APD • ASIC integrates & shapes 32 signal channels from APD • Selectable risetime & falltime constants • ASIC’s 8: 1 Multiplexers run @ 16 MHz to sample each channel at 500 ns/sample • ASIC’s four outputs are continuously digitized by quad ADC (AD 41240 CERN/”Chip. Ideas”) and sent to FPGA • ~ 20, 000 FEBs in NOv. A Far Detector (~ 1 per ton of detector) 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 4

f r T 8 f 17 - 20 May, 2006 T r T 8

f r T 8 f 17 - 20 May, 2006 T r T 8 T f T r 8: 1 Mux r T 8 T • 16 MHz multiplexers • 2 Msps per channel • Adjustable risetime & falltime 8: 1 Mux 8 f 8: 1 Mux T 8: 1 Mux 32 ch ASIC (See talk by Tom Zimmerman) FEE 2006 / Perugia, Italy 5

DAQ Heirarchy – 64 FEBs to one “Data Concentrator FEBs Beam Power Distribution 17

DAQ Heirarchy – 64 FEBs to one “Data Concentrator FEBs Beam Power Distribution 17 - 20 May, 2006 Data Concentrator FEE 2006 / Perugia, Italy DAQ 6

DAQ Heirarchy – con’t DCM DAQ & Timing DCM • 324 Data Concentrators connected

DAQ Heirarchy – con’t DCM DAQ & Timing DCM • 324 Data Concentrators connected to CPU Farm via ethernet switches & timing cables. • All pixel hit data sent through Concentrators to CPU farm – Timing signal take reverse path • Each “hit” 32 bit timestamp (62. 5 ns / bin, synched to Global timing system) + pulseheight • Global timing system with GPS receiver to correlate timing with NUMI beam spills • All data are buffered for ~ 10 seconds • NUMI beamline spill is GPS timestamped & transmitted to Far Detector via internet (as is now done in MINOS) • 90% - 95% of timestamps arrive within 1 sec. Efficiency is ~ 100% in < 10 sec. 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 7

Signal Processing - Pulseheight Sampled waveform g(x) g(n) 6 5 4 3 2 1

Signal Processing - Pulseheight Sampled waveform g(x) g(n) 6 5 4 3 2 1 0 1 2 3 4 5 6 • Use multiple correlated pairs of samples centered on leading edge • Weight the pairs by optimal coefficients • Optimal coefficients depend on noise spectrum Ø Parallel noise favors inner pair (small sampling time, small no of samples) Ø Series noise favors multiples pairs (long risetime constant, large number of samples) 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 8

Signal Processing – Pulseheight (con’t) • In general FIR filter with modest (2 –

Signal Processing – Pulseheight (con’t) • In general FIR filter with modest (2 – 8) number of coefficients • Easily implemented in FPGA (multipliers, accumulators) • Coefficients “learned” by DSO (Digital Oscilloscope) mode during calibration • Take ~ 1 ms sample of baseline @ 500 ns / sample (2 k points 4 k bytes) • Analysis of baseline noise yields Ø Equivalent APD leakage current Compute enc vs DT using dual correlated sampling and fit to sqrt(DT) Ø Amplifier equivalent input noise density, en Compute enc vs risetime and fit to 1/sqrt(TR) Ø Optimal filter coefficients (from noise autocorrelation function) 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 9

Filter simulation & testing • Synthesize signals and noise traces parameterized by Ø Equivalent

Filter simulation & testing • Synthesize signals and noise traces parameterized by Ø Equivalent APD leakage current, IL Ø Equivalent preamp input noise density en Ø Pulseheight, risetime & falltime constants Ø Noise trace synthesis done by numerical integration (iterate finite diff eqn) • Baseline noise and signals from prototype electronics ( Can’t “dial” noise components ) 100 us 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 10

Example : Quad sampling with • 1 st pair DT = 1 us •

Example : Quad sampling with • 1 st pair DT = 1 us • 2 nd pair DT = 3 us • Variable weighting factor 0 < a < 1 • Optimal point a ~ 0. 4 • Data taken from prototype electronics so can’t choose noise components • Result is ~ 20% improvement over DCS with prototype electronics (not ASIC) • In practice, 6 – 8 terms works well 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 11

Timing extraction • Trailing edge contains as much timing information as the leading edge

Timing extraction • Trailing edge contains as much timing information as the leading edge • Timing extraction by “matched filtering” • FIR filter performs correlation of “ideal” pulse shape with incoming pulse • Filter output is ~ symmetrical signal whose peak is a measure of time of arrival • Peak is found by “interpolation” filter (“upsampling”) 40 us 100 us 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 12

Interpolation (“upsampling”) 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 13

Interpolation (“upsampling”) 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 13

Timing resolution vs pulseheight (SNR) NOv. A “Worst case” SNR NOv. A “Typical” SNR

Timing resolution vs pulseheight (SNR) NOv. A “Worst case” SNR NOv. A “Typical” SNR • Measurements made with test electronics • Final results will depend on APD/ASIC noise spectrum 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 14

Triggering • Triggering is done on output of pulseheight filter • Pulse shape discrimination

Triggering • Triggering is done on output of pulseheight filter • Pulse shape discrimination “Signal don’t look like noise” • Noise hits tend to stay over threshold for 1 clock duration only • Triggering on signal over threshold for 2 clock cycles can reduce noise hit rate by 10 x 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 15

NOv. A Near Detector Readout • Near Detector is small version of Far Detector

NOv. A Near Detector Readout • Near Detector is small version of Far Detector • Location (End of NUMI beam line @ Fermilab) • Shorter cells higher photoelectron yield much better SNR ( > 2 x) • Very low cosmic ray rates ( ~ 100 meters earth overburden) • Very high rate of beam events in 10 us spill • Initial simulations ~ 50 direct + 150 rock muon events per spill • High probability of event overlaps in detector • Requirements under study (simulations) but likely “several” microsecond 2 -track separation • Best case scenario Ø Maintain 500 ns sampling, filter modifications for good 2 -track separation, take advantage of better SNR Ø Firmware modifications only • Worst case scenario Ø Increase sampling to 250 ns or less. Ø ASIC mods 4: 1 multiplexing Ø 2 or more ADCs per board • Other scenarios under study 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 16

Conclusions • • Flexible architecture : Continuous digitization + DSP Ø 2 MSPS DSO

Conclusions • • Flexible architecture : Continuous digitization + DSP Ø 2 MSPS DSO on every channel : Local analysis in FPGA Ø Algorithms optimized in-situ for pulseheight & timing Ø In-situ diagnostics: Opens, shorts, APD high voltage, etc NUMI beam spill signal not required “in-time” at FEBs Ø Spill signal sent to Far Detector via internet after spill Ø All in-spill data sorted for time-stamp and saved to disc Low cost Front End Electronics 1 FEB ~ 100 Euro 1 ton of detector Un-advertised science bonus : If supernova occurs in our galaxy, NOv. A will see it clearly : ~ 1, 000 s of neutrinos detected within 10 – 20 sec. with characteristic time structure. ( ~1% prob/yr ) 17 - 20 May, 2006 FEE 2006 / Perugia, Italy 17