FPGA Implementation of a MessagePassing OFDM Receiver for

FPGA Implementation of a Message-Passing OFDM Receiver for Impulsive Noise Channels Karl F. Nieman†, Marcel Nassar‡, Jing Lin†, and Brian L. Evans† †Wireless Communications and Networks Group, The University of Texas at Austin, TX ‡Mobile Solutions Lab, Samsung Information Systems America, San Diego, CA IEEE Asilomar Conference on Signals, Systems, and Computers Pacific Grove, CA November 6, 2013

Smart Grid Communications Communication backhaul carries traffic between concentrator and utility on wired or Data wireless links concentrator Local utility Medium Voltage (MV) 1 k. V – 33 k. V Low voltage (LV) < 1 k. V Smart meters MV-LV transformer Smart meter communications between smart meters and data concentrator via powerline or wireless links Home area data networks connect appliances, EV charger and smart meter via powerline or wireless links Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 2

Impulsive Noise in 3 -200 k. Hz PLC Band Outdoor medium-voltage line (St. Louis, MO) Indoor low-voltage line (UT Campus) Interleave Cyclostationary noise becomes asynchronous after interleaving Impulsive noise can be 40 d. B above background noise Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 3

Impulsive Noise in OFDM Systems Receiver IFFT Vector of symbol amplitudes (complex) Filter + FFT Equalizer and detector Channel FFT spreads received impulsive noise across all FFT bins – SNR of each FFT bin is decreased – Receiver communication performance degrades Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 4

Impulsive Noise Mitigation (Denoising) Receiver IFFT Vector of symbol amplitudes (complex) • Filter + Channel + - Impulsive noise estimation FFT + Equalizer and detector Conventional OFDM system Added in our system Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 5

Impulsive Noise Mitigation Techniques • Compressive sensing approaches are used for low SNR • AMP provides best performance vs. complexity tradeoff compressive sensing Method Low SNR High SNR Non. Parametric? Computational Complexity Nulling/ Clipping[Tse 12] Low Thresholded Least Squares/MMSE[Cai 08] Med Sparse Bayesian Learning[Lin 13] High (matrix inversion) l 1 -norm minimization[Cai 08] High Approximate Message Passing (AMP) [Nas 13] Med Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 6

Approximate Message Passing (AMP) 1. Initialization 2. Output Linear 3. Output Non-Linear • M = null tones • N = FFT size • Iterate – Time-frequency projections 5. Input Non-Linear 4. Input Linear • Mostly scalar arithmetic and data • Parallelizable for hardware implementation – FFT/IFFT, exponential, vector multiplies, divisions Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 7

Synchronous Dataflow (SDF) Model • Targeted architecture for real-time streaming performance: – Xilinx Virtex V field programmable gate arrays (FPGAs) – Embedded x 86 computers running real-time OS (Phar Lap ETS) Task Processing • SDF model of OFDM receiver with AMP noise mitigation: • Periodic schedule is O Input samples from ADC A Resampling FIR filters B Time and Freq. Offset Correction C FFT + Index Active and Null Subcarriers D AMP Noise Estimation E FFT + Index Active Subcarriers F Subtract Noise Estimate, De-Interleave Reference Symbols H Zero-Forcing Equalization I Equalize and Detect Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 8

Mapping AMP to Fixed-Point • Variables sized using MATLAB Fixed-Point Toolbox • Most variables sized within 16 -bit wordlengths Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 9

Graphical High-Level FPGA Synthesis National Instruments Communication System Design Tools – Lab. VIEW DSP Design Module – Lab. VIEW FPGA – Lab. VIEW Real-Time 2. Output Linear Step 2 of AMP DSP diagram replaces thousands of lines of VHDL code Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 10

AMP-Enhanced OFDM Testbed TX Chassis RX Chassis 1 × PXIe-1082 1 × PXIe-8133 1 × PXIe-7965 R 1 × NI-5781 FAM 1 × PXIe-1082 1 × PXIe-8133 2 × PXIe-7965 R 1 × NI-5781 FAM differential MCX pair (quadrature component = 0) differential MCX pair 16 -bit DAC sample rate conversi on 256 IFFT w/ 22 CP insertion zero padding (null tones) generat e complex conjuga te pair data and referenc e symbol interleav e Ref. symbol LUT Lab. VIEW DSP Design Module NI 5781 14 -bit ADC NI 5781 Flex. RIO FPGA Module 1 (G 3 TX) sample rate conversi on time and frequen cy offset correcti on 256 FFT w/ 22 CP remova l, noise injectio n Lab. VIEW DSP Design Module Flex. RIO FPGA Module 2 (G 3 RX) null tone and active tone separatio n testbench control/data visualization data symbol generation AMP noise estimate 256 FFT, tone select Lab. VIEW RT RT controller Subtract noise estimate from active tones data and reference symbol deinterleav e Lab. VIEW Host Computer channel estimatio n/ ZF equalizat ion Lab. VIEW DSP Design Module Flex. RIO FPGA Module 3 (AMPEQ) BER/SNR calculation w/ and w/o AMP Lab. VIEW RT RT controller Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 11

Results • Received QPSK constellation at equalizer output Resource Utilization FPGA conventional receiver with AMP Trans. Rec. AMP+Eq 1 2 3 total slices 32. 6% 64. 0% 94. 2% slice reg. 15. 8% 39. 3% 59. 0% slice LUTs 17. 6% 42. 4% 71. 4% DSP 48 s 2. 0% 7. 3% 27. 3% block. RAMs 7. 8% 18. 4% 29. 1% Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 12

Bit-Error-Rate Measurements uncoded bit-error-rate (BER) 8 d. B for 30 d. B impulsive noise 4 d. B for 20 d. B impulsive noise No loss (or gain) in non-impulsive (AWGN) noise signal-to-noise ratio (SNR) Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 13

Conclusions • Approximate Message Passing Framework allows – Impulsive noise mitigation at low and high SNR – Conversion of matrix operations to scalar and vector operations – Parallelization and efficient mapping to hardware • Up to 8 d. B impulsive noise mitigation achieved using – Fixed-point data and arithmetic – Streaming G 3 -PLC rates • Lab. VIEW project and FPGA bitfiles available here: – http: //users. ece. utexas. edu/~bevans/papers/2013/fpga. Receiver/index. html Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 14

References [Cai 08] – G. Caire; T. Y. Al-Naffouri; A. K. Narayanan, "Impulse noise cancellation in OFDM: an application of compressed sensing, " Information Theory, 2008. ISIT 2008. IEEE International Symposium on , 2008. [Tse 12] – D-F. Tseng; Y. S. Han; W. H. Mow; L-C. Chang; A. J. H. Vinck, "Robust Clipping for OFDM Transmissions over Memoryless Impulsive Noise Channels, " Communications Letters, IEEE , vol. 16, no. 7, 2012. [Lin 13] – J. Lin; M. Nassar; B. L. Evans, "Impulsive Noise Mitigation in Powerline Communications Using Sparse Bayesian Learning, " Selected Areas in Communications, IEEE Journal on , vol. 31, no. 7, 2013. [Nas 13] – M. Nassar; P. Schniter; B. L. Evans, "A factor graph approach to joint OFDM channel estimation and decoding in impulsive noise environments, " IEEE Trans. on Signal Processing, accepted for publication, 2013. [Max 11] – Maxim and ERDF, "Open Standard for Smart Grid Implementation, " 2011. 15

Questions? 16

Backup Slides 17

Powerline Communications (PLC) Bit Rates Coverag e Categories Band Narrowban d • (ITU) PRIME, Multi. Smart meter 3 -500 up to G 3 kilomete communicati k. Hz 800 kbps • ITU-T G. hnem r on • IEEE P 1901. 2 1. 8 -250 Broadband MHz up to 200 Mbps <1500 m Enables Standards Home area • Home. Plug data • ITU-T G. hn networks • IEEE P 1901 • Uses orthogonal frequency-division multiplexing (OFDM) • Communication challenges – Channel distortions – Non-Gaussian impulsive noise Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 18

Background | System Design and Implementation | Demo | Conclusion AMPEQ. lvdsp (first half) (second half) 19

Approximate Message Passing (AMP) • Reconstruct time-domain noise from frequencydomain null tones • Iterate until convergence • Algorithm consists of: • Mostly scalar arithmetic • FFT/IFFTs • Exponential • Targeted at G 3 -PLC signaling structure Background | Impulsive Noise Mitigation | Mapping to Hardware | Implementation 20