Four Fundamental Operating System Concepts Sam Kumar CS

Recall: What is an Operating System? • Special layer of software that provides application

Recall: OS Abstracts the Underlying Hardware Compiled Program System Libs Process: Execution environment with

Recall: OS Protects Processes and the Kernel Segmentation fault Compiled (core dumped) Program 1

Recall: What is an Operating System? • Referee • Manage protection, isolation, and sharing

Today: Four Fundamental OS Concepts • Thread: Execution Context • Program Counter, Registers, Execution

OS Bottom Line: Run Programs Program Source Compiler and Linker Executable OS data stack

Review (61 C): How Programs Execute next Processor Memory PC: instruction Instruction fetch Decode

Review (61 C): How Programs Execute Addr 232 -1 R 0 … R 31

Key OS Concept: Thread • Definition: A single, unique execution context • Program counter,

Illusion of Multiple Processors v. CPU 1 v. CPU 2 • Threads are virtual

OS Object Representing a Thread • Traditional term: Thread Control Block (TCB) • Holds

Registers: RISC-V → x 86 Load/Store Arch with software conventions Complex mem-mem arch with

Illusion of Multiple Processors v. CPU 1 v. CPU 2 • At T 1:

Very Simple Multiprogramming • All v. CPUs share non-CPU resources • Memory, I/O Devices

Key OS Concept: Address Space • Program operates in an address space that is

Address Space • Definition: Set of accessible addresses and the state associated with them

Typical Address Space Structure 0 x 000… Code PC: SP: Static Data Heap Processor

What can hardware do to help the OS protect itself from programs? And programs

Base and Bound (no Translation) • Requires relocation • Can the program touch OS?

Base and Bound (with Translation) 0000… • Can the program touch OS? • Can

Paged Virtual Address Space • What if we break the entire virtual address space

Paged Virtual Address Space Memory Processor Registers <Page #> Page Table <Frame Addr> instruction

Key OS Concept: Process • Definition: execution environment with restricted rights • One or

Single and Multithreaded Processes • Threads encapsulate concurrency • “Active” component • Address space

Protection and Isolation • Why? • Reliability: bugs can only overwrite memory of process

Dual-Mode Operation • One bit of state: processor is either in (user mode or

Announcements • Homework 0 is out! • Due Thursday • Register for the autograder

Dual-Mode Operation • Processes (i. e. , programs you run) execute in user mode

Three Types of User → Kernel Mode Transfer • System Call (“syscalls”) • Process

interrupt number (i) Where do User → Kernel Mode Transfers Go? Address and properties

Example: Before Exception 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 37

Example: After Exception Why don’t we just use the user stack? 10/24/2021 Kumar CS

Life of a Process User Mode syscall rtn interrupt exception rfi exec Limited HW

Implementing Safe User → Kernel Mode Transfers • Carefully constructed kernel code packs up

Kernel System Call Handler • Vector through well-defined syscall entry points! • Table mapping

Kernel Stacks • Interrupt handlers want a stack • System call handlers want a

Kernel Stacks • One Solution: two-stack model • Each thread has user stack and

Hardware Support: Interrupt Control • Interrupt processing not visible to the user process: •

How do we take Interrupts Safely? • Interrupt vector • Limited number of entry

Kernel → User Mode Transfers • “Return from interrupt” instruction • Drops mode from

Break (If Time) 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 49

Now, let’s put it all together! 10/24/2021 Kumar CS 162 at UC Berkeley, Summer

Scheduling if ( ready. Processes(PCBs) ) { next. PCB = select. Process(PCBs); run( next.

What’s in a Process? • Process Control Block (PCB): Kernel representation of each process

Mode Transfer and Translation • Mode transfer should change address translation mapping • Examples:

Base and Bound: OS Loads Process Proc 1 Proc 2 … code Proc n

Base and Bound: About to Switch Proc 1 Proc 2 … code Proc n

Base and Bound: User Code Running Proc 1 Proc 2 … code Proc n

Base and Bound: Handle Interrupt Proc 1 Proc 2 … code Proc n 0000…

Base and Bound: Switch to Process 1 Proc 2 … code Proc n 0000…

Putting it all Together: Web Server 4. parse request Server request buffer 1. network

Conclusion: Four Fundamental OS Concepts • Thread: Execution Context • Program Counter, Registers, Execution

Slides: 62

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Four Fundamental Operating System Concepts Sam Kumar CS 162: Operating Systems and System Programming Lecture 2 https: //inst. eecs. berkeley. edu/~cs 162/su 20 Read: A&D, 2. 1 -7 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 1

Recall: What is an Operating System? • Special layer of software that provides application software access to hardware resources • • Convenient abstraction of complex hardware devices Protected access to shared resources appln Security and authentication appln Communication OS Hardware 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 2

Recall: OS Abstracts the Underlying Hardware Compiled Program System Libs Process: Execution environment with restricted rights provided by OS Threads Address Spaces Files Sockets Operating System ISA Hardware Processor Pg. Tbl & TLB Memory OS Mem Networks Storage I/O Ctrlr 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 3

Recall: OS Protects Processes and the Kernel Segmentation fault Compiled (core dumped) Program 1 Compiler Threads Program 2 System Libs Process 1 Process 2 Address Spaces Files Sockets Threads Address Spaces Files Sockets Operating System ISA Hardware Processor Pg. Tbl & TLB Memory OS Mem Networks Storage I/O Ctrlr 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 4

Recall: What is an Operating System? • Referee • Manage protection, isolation, and sharing of resources • Resource allocation and communication • Illusionist • Provide clean, easy-to-use abstractions of physical resources • Infinite memory, dedicated machine • Higher level objects: files, users, messages • Masking limitations, virtualization • Glue • Common services • Storage, Window system, Networking • Sharing, Authorization • Look and feel 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 5

Today: Four Fundamental OS Concepts • Thread: Execution Context • Program Counter, Registers, Execution Flags, Stack • Address Space (with Translation) • Program’s view of memory is distinct from physical machine • Process: Instance of a Running Program • Address space + one or more threads + … • Dual-Mode Operation and Protection • Only the “system” can access certain resources • Combined with translation, isolates programs from each other 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 6

OS Bottom Line: Run Programs Program Source Compiler and Linker Executable OS data stack instructions foo. c OS Loader data a. out • Create OS “PCB”, address space, stack and heap • Load instruction and data segments of executable file into memory • “Transfer control to program” • Provide services to program • While protecting OS and program 10/24/2021 heap Kumar CS 162 at UC Berkeley, Summer 2020 Memory Editor int main() {…; } 0 x. FFF… instructions 0 x 000… PC: registers Processor 7

OS Bottom Line: Run Programs Program Source Compiler and Linker Executable OS data stack instructions foo. c OS Loader data a. out • Create OS “PCB”, address space, stack and heap • Load instruction and data segments of executable file Creates a process into memory • “Transfer control to program” from a program • Provide services to program • While protecting OS and program 10/24/2021 heap Kumar CS 162 at UC Berkeley, Summer 2020 Memory Editor int main() {…; } 0 x. FFF… instructions 0 x 000… PC: registers Processor 8

Review (61 C): How Programs Execute next Processor Memory PC: instruction Instruction fetch Decode decode Registers Execute ALU data 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 9

Review (61 C): How Programs Execute Addr 232 -1 R 0 … R 31 F 0 … F 30 PC Fetch Exec … Data 1 Data 0 Inst 237 Inst 236 … Inst 4 Inst 3 Inst 2 Inst 1 Inst 0 Addr 0 10/24/2021 • Execution sequence: • • • Fetch Instruction at PC Decode Execute (possibly using registers) Write results to registers/mem PC = Next Instruction(PC) Repeat PC PC Kumar CS 162 at UC Berkeley, Summer 2020 10

Key OS Concept: Thread • Definition: A single, unique execution context • Program counter, registers, stack • A thread is the OS abstraction for a CPU core • A “virtual CPU” of sorts • Registers hold the root state of the thread: • Including program counter – pointer to the currently executing instruction • The rest is “in memory” • Registers point to thread state in memory: • Stack pointer to the top of the thread’s (own) stack 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 12

Illusion of Multiple Processors v. CPU 1 v. CPU 2 • Threads are virtual cores • Multiple threads: Multiplex hardware in time • A thread is executing on a processor when it is resident in that processor's registers v. CPU 3 Shared Memory On a single physical CPU: v. CPU 1 v. CPU 2 Time 10/24/2021 v. CPU 3 v. CPU 1 v. CPU 2 • Each virtual core (thread) has PC, SP, Registers • Where is it? • On the real (physical) core, or • Saved in memory – called the Thread Control Block (TCB) Kumar CS 162 at UC Berkeley, Summer 2020 13

OS Object Representing a Thread • Traditional term: Thread Control Block (TCB) • Holds contents of registers when thread is not running… • … And other information the kernel needs to keep track of the thread and its state. 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 14

Registers: RISC-V → x 86 Load/Store Arch with software conventions Complex mem-mem arch with specialized registers and “segments” • In CS 61 C you learned RISC-V • In section tomorrow you’ll learn x 86 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 15

Illusion of Multiple Processors v. CPU 1 v. CPU 2 • At T 1: v. CPU 1 on real core • At T 2: v. CPU 2 on real core v. CPU 3 Shared Memory • What happened? On a single physical CPU: T 1 T 2 v. CPU 1 v. CPU 2 Time 10/24/2021 v. CPU 3 v. CPU 1 • OS ran [how? ] • Saved PC, SP, … in v. CPU 1’s thread control block • Loaded PC, SP, … from v. CPU 2’s thread control block v. CPU 2 • This is called context switch Kumar CS 162 at UC Berkeley, Summer 2020 16

Very Simple Multiprogramming • All v. CPUs share non-CPU resources • Memory, I/O Devices • Each thread can read/write memory • Including data of others • And the OS! • Unusable? • This approach is used in: • • Very early days of computing Embedded applications Mac. OS 1 -9/Windows 3. 1 (switch only with voluntary yield) Windows 95 -ME 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 17

Key OS Concept: Address Space • Program operates in an address space that is distinct from the physical memory space of the machine 0 x 000… Processor Registers Translator Memory 0 x. FFF… 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 19

Address Space • Definition: Set of accessible addresses and the state associated with them • 232 = ~4 billion on a 32 -bit machine • What happens when you read or write to an address? • Perhaps acts like regular memory • Perhaps causes I/O operation • (Memory-mapped I/O) • Causes program to abort (segfault)? • Communicate with another program • … 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 0 x 000… Code Static Data Heap Stack 0 x. FFF… 20

Typical Address Space Structure 0 x 000… Code PC: SP: Static Data Heap Processor registers Stack 0 x. FFF… 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 21

What can hardware do to help the OS protect itself from programs? And programs from each other? 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 22

Base and Bound (no Translation) • Requires relocation • Can the program touch OS? • Can it touch other programs? Base Address Code Static Data Heap Original Program Stack 1000… ≥ 0010… Program 1010… address 0000… Code 1000… Static Data code 0000… Static Data heap Heap Bound 0100… < stack Stack 1100… 0100… FFFF… 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 23

Base and Bound (with Translation) 0000… • Can the program touch OS? • Can it touch other programs? • Fragmentation still an issue! Code Static Data Heap Original Program Stack 0010… Program 0010… address Base Address 1000… Code 1010… Bound 0100… < 1000… Static Data code 0000… Static Data heap Heap stack Stack 1100… 0100… FFFF… 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 24

Paged Virtual Address Space • What if we break the entire virtual address space into equal-size chunks (i. e. , pages) and have a base and bound for each? • All pages same size, so easy to place each page in memory! • Hardware translates address using a page table • Each page has a separate base • The “bound” is the page size • Special hardware register stores pointer to page table 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 25

Paged Virtual Address Space Memory Processor Registers <Page #> Page Table <Frame Addr> instruction <Virtual Address> = <Page #> <Page Offset> Page (eg, 4 kb) PT Addr • Instructions operate on virtual addresses • Translated at runtime to physical addresses via a page table • Special register holds page table base address of current process’ page table 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 26

Key OS Concept: Process • Definition: execution environment with restricted rights • One or more threads executing in a single address space • Owns file descriptors, network connections • Instance of a running program • When you run an executable, it runs in its own process • Application: one or more processes working together • Protected from each other; OS protected from them • In modern OSes, anything that runs outside of the kernel runs in a process 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 28

Single and Multithreaded Processes • Threads encapsulate concurrency • “Active” component • Address space encapsulate protection: • “Passive” component • Keeps bugs from crashing the entire system • Why have multiple threads per address space? 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 29

Protection and Isolation • Why? • Reliability: bugs can only overwrite memory of process they are in • Security and privacy: malicious or compromised process can’t read or write other process’ data • (to some degree) Fairness: enforce shares of disk, CPU • Mechanisms: • Address translation: address space only contains its own data • BUT: why can’t a process change the page table pointer? • Or use I/O instructions to bypass the system? • Hardware must support privilege levels 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 30

Dual-Mode Operation • One bit of state: processor is either in (user mode or kernel mode) • Certain actions are only permitted in kernel mode • e. g. , changing the page table pointer • Certain entries in the page table • Hardware I/O instructions 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 32

Announcements • Homework 0 is out! • Due Thursday • Register for the autograder and get the class VM running ASAP • Quiz 0 is tomorrow • Optional, ungraded • Opportunity to get familiar with online exam format • If you have a conflict with any of the exams, then fill out the Exam Conflict Form linked on Piazza 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 33

Dual-Mode Operation • Processes (i. e. , programs you run) execute in user mode • To perform privileged actions, processes request services from the OS kernel • Carefully controlled transition from user to kernel mode • Kernel executes in kernel mode • Performs privileged actions to support running processes • … and configures hardware to properly protect them (e. g. , address translation) 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 34

Three Types of User → Kernel Mode Transfer • System Call (“syscalls”) • Process requests a system service (e. g. , open a file) • Like a function call, but “outside” the process • Interrupt • External asynchronous event, independent of the process • e. g. , Timer, I/O device • Trap • Internal synchronous event in process triggers context switch • E. g. , Divide by zero, bad memory access (segmentation fault) 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 All 3 exceptions are UNPROGRAMMED CONTROL TRANSFER • User process can’t jump to arbitrary instruction address in kernel! • Why not? 35

interrupt number (i) Where do User → Kernel Mode Transfers Go? Address and properties of each interrupt handler intrp. Handler_i () { … } 10/24/2021 • Cannot let user programs specify the exact address! • Solution: Interrupt Vector • OS kernel specifies a set of functions that are entrypoints to kernel mode • Appropriate function is chosen depending on the type of transition Kumar CS 162 at UC Berkeley, Summer 2020 • Interrupt Number (i) • OS may do additional dispatch 36

Example: Before Exception 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 37

Example: After Exception Why don’t we just use the user stack? 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 38

Life of a Process User Mode syscall rtn interrupt exception rfi exec Limited HW access 10/24/2021 Kernel Mode exit Full HW access Kumar CS 162 at UC Berkeley, Summer 2020 39

Implementing Safe User → Kernel Mode Transfers • Carefully constructed kernel code packs up the user process state and sets it aside • Must handle weird/buggy/malicious user state • Syscalls with null pointers • Return instruction out of bounds • User stack pointer out of bounds • Should be impossible for buggy or malicious user program to cause the kernel to corrupt itself • User program should not know that an interrupt has occurred (transparency) 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 40

Kernel System Call Handler • Vector through well-defined syscall entry points! • Table mapping system call number to handler • Locate arguments • In registers or on user (!) stack • Copy arguments • From user memory into kernel memory – carefully checking locations! • Protect kernel from malicious code evading checks • Validate arguments • Protect kernel from errors in user code • Copy results back • Into user memory – carefully checking locations! 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 41

Kernel Stacks • Interrupt handlers want a stack • System call handlers want a stack • Can't just use the user stack [why? ] 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 42

Kernel Stacks • One Solution: two-stack model • Each thread has user stack and a kernel stack • Kernel stack stores users registers during an exception • Kernel stack used to execute exception handler in the kernel 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 43

Hardware Support: Interrupt Control • Interrupt processing not visible to the user process: • Occurs between instructions, restarted transparently • No change to process state • Happens transparently to the process—user program does not know it was interrupted • Interrupt Handler invoked with interrupts ‘disabled’ • Re-enabled upon completion • Non-blocking (run to completion, no waits) • Pack up in a queue and pass off to an OS thread for hard work • wake up an existing OS thread 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 44

Hardware Support: Interrupt Control • Interrupt processing not visible to the user process: • Occurs between instructions, restarted transparently • No change to process state • What can be observed even with perfect interrupt processing? • Interrupt Handler invoked with interrupts ‘disabled’ • Re-enabled upon completion • Non-blocking (run to completion, no waits) • Pack up in a queue and pass off to an OS thread for hard work • wake up an existing OS thread 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 45

How do we take Interrupts Safely? • Interrupt vector • Limited number of entry points into kernel • Kernel interrupt stack • Handler works regardless of state of user code • Interrupt masking • Handler is non-blocking • Atomic transfer of control • “Single instruction”-like to change: • • Program counter Stack pointer Memory protection Kernel/user mode • Transparent restartable execution • User program does not know interrupt occurred 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 46

Kernel → User Mode Transfers • “Return from interrupt” instruction • Drops mode from kernel to user privilege • Restores user PC and stack 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 47

Break (If Time) 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 49

Now, let’s put it all together! 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 50

Illusion of Multiple Processors v. CPU 1 v. CPU 2 • At T 1: v. CPU 1 on real core • At T 2: v. CPU 2 on real core v. CPU 3 Scheduling Shared Memory • How did the OS get to run? On a single physical CPU: T 1 T 2 v. CPU 1 v. CPU 2 Time 10/24/2021 v. CPU 3 v. CPU 1 v. CPU 2 • Earlier, OS configured a hardware timer to periodically generate an interrupt • On the interrupt, the hardware switches to kernel mode and the OS’s timer interrupt handler runs • Timer interrupt handler decides whether to switch threads or not according to a policy Kumar CS 162 at UC Berkeley, Summer 2020 51

Scheduling if ( ready. Processes(PCBs) ) { next. PCB = select. Process(PCBs); run( next. PCB ); } else { run_idle_process(); } • Scheduling: Mechanism for deciding which processes/threads receive the CPU • Lots of different scheduling policies provide … • Fairness or • Realtime guarantees or • Latency optimization or … 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 52

What’s in a Process? • Process Control Block (PCB): Kernel representation of each process • Process ID • Thread control block(s) • Program pointer, stack pointer, and registers for each thread • Page table (information for address space translation) • Necessary state to process system calls • Which files are open and which network connections are accessible to the process 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 53

Mode Transfer and Translation • Mode transfer should change address translation mapping • Examples: • Ignore base and bound in kernel mode • Page tables: • Either switch to kernel page table… • Or mark some pages as only accessible in kernel mode 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 54

Base and Bound: OS Loads Process Proc 1 Proc 2 … code Proc n 0000… Static Data heap OS stack sysmode 1 code Base xxxx … 0000… Static Data Bound xxxx… FFFF… heap Stored User PC xxxx… stack PC code regs 1100… 3000… Static Data … heap stack 10/24/2021 1000… Kumar CS 162 at UC Berkeley, Summer 2020 3080… FFFF… 55

Base and Bound: About to Switch Proc 1 Proc 2 … code Proc n 0000… Static Data heap OS stack sysmode code Base 1000 … 0000… Static Data Bound 1100 … FFFF… heap Stored User PC 0011 … • OS runs in privileged mode, so it can set the special registers • “Return” to user 10/24/2021 1 stack PC code regs 1000… 1100… 3000… Static Data … heap stack Kumar CS 162 at UC Berkeley, Summer 2020 3080… FFFF… 56

Base and Bound: User Code Running Proc 1 Proc 2 … code Proc n 0000… Static Data heap OS stack sysmode 0 code Base 1000 … Static Data Bound 1100 … heap Stored User PC xxxx … stack PC code regs 1100… 3000… Static Data … heap stack 10/24/2021 1000… Kumar CS 162 at UC Berkeley, Summer 2020 3080… FFFF… 57

Base and Bound: Handle Interrupt Proc 1 Proc 2 … code Proc n 0000… Static Data heap OS stack sysmode code Base 1000 … 0000… Static Data Bound 1100 … FFFF… heap Stored User PC • Switch to kernel mode, set up interrupt handler 1 PC 0000 1234 stack Intrp. Vector[i] code regs 1100… 3000… Static Data … heap stack 10/24/2021 1000… Kumar CS 162 at UC Berkeley, Summer 2020 3080… FFFF… 58

Base and Bound: Switch to Process 1 Proc 2 … code Proc n 0000… RTU Static Data heap OS stack sysmode code Base 3000 … 0000… Static Data Bound 0080 … FFFF… heap Stored User PC 0000 0248 PC 0001 0124 • Save registers of Process 2 • Restore registers of Process 1 • Then execute RTU 10/24/2021 1 stack code regs 1000… 1100… 3000… Static Data … heap stack Kumar CS 162 at UC Berkeley, Summer 2020 3080… FFFF… 59

Base and Bound: Switch to Process 1 Proc 2 … code Proc n 0000… Static Data heap OS stack sysmode 1 code Base 3000 … Static Data Bound 0080 … heap Stored User PC xxxx … PC stack 0000 0248 code regs 1100… 3000… Static Data … heap stack 10/24/2021 1000… Kumar CS 162 at UC Berkeley, Summer 2020 3080… FFFF… 60

Putting it all Together: Web Server 4. parse request Server request buffer 1. network socket syscall read interrupt Hardware reply buffer 3. kernel copy RTU Kernel wait 10/24/2021 9. format reply 10. network 5. file socket write syscall read Network interface Request RTU 11. kernel copy from user buffer to network buffer 2. copy arriving 12. format outgoing packet (DMA) packet and DMA 8. kernel copy 6. disk request interrupt 7. disk data (DMA) Disk interface Reply Kumar CS 162 at UC Berkeley, Summer 2020 61

Conclusion: Four Fundamental OS Concepts • Thread: Execution Context • Program Counter, Registers, Execution Flags, Stack • Address Space (with Translation) • Program’s view of memory is distinct from physical machine • Process: Instance of a Running Program • Address space + one or more threads + … • Dual-Mode Operation and Protection • Only the “system” can access certain resources • Combined with translation, isolates programs from each other 10/24/2021 Kumar CS 162 at UC Berkeley, Summer 2020 62