Foundation of Systems Xiang Lian The University of

Foundation of Systems Xiang Lian The University of Texas-Pan American

Chapter 4 The Processor

§ 4. 1 Introduction n CPU performance factors n Instruction count n n CPI and Cycle time n n Determined by CPU hardware We will examine two MIPS implementations n n n Determined by ISA and compiler A simplified version A more realistic pipelined version Simple subset, shows most aspects n n n Memory reference: lw, sw Arithmetic/logical: add, sub, and, or, slt Control transfer: beq, j Chapter 4 — The Processor — 3

Instruction Execution n PC instruction memory, fetch instruction Register numbers register file, read registers Depending on instruction class n Use ALU to calculate n n n Arithmetic result Memory address for load/store Branch target address Access data memory for load/store PC target address or PC + 4 Chapter 4 — The Processor — 4

CPU Overview Chapter 4 — The Processor — 5

Multiplexers n Can’t just join wires together n Use multiplexers Chapter 4 — The Processor — 6

Control Chapter 4 — The Processor — 7

n Information encoded in binary n n Combinational element n n n Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses § 4. 2 Logic Design Conventions Logic Design Basics Operate on data Output is a function of input State (sequential) elements n Store information Chapter 4 — The Processor — 8

Combinational Elements n AND-gate n Y=A&B A B n Adder n A + Y=A+B Y Multiplexer n n Y = S ? I 1 : I 0 I 1 M u x S n Arithmetic/Logic Unit n Y = F(A, B) A ALU Y Y B F Chapter 4 — The Processor — 9

Example: Combinational Elements 0011 n AND-gate n n Y=A&B 0011 n 0101 Y=A+B + Y B Y 0101 Multiplexer n 1000 A 0001 A B n Adder Y = S ? I 1 : I 0 0011 I 0 I 1 M u x Y 0101 S 1 n Arithmetic/Logic Unit n Y = F(A, B) 0011 A 0101 ALU Y 0111 B 0101 F or Chapter 4 — The Processor — 10

Sequential Elements n Register: stores data in a circuit n n Uses a clock signal to determine when to update the stored value Edge-triggered: update when Clk changes from 0 to 1 Clk D Clk Q 0011 1000 D Q 0011 1000 Chapter 4 — The Processor — 11

Sequential Elements n Register with write control n n Only updates on clock edge when write control input is 1 Used when stored value is required later Clk D Write Clk Q Write 0011 1000 D Q 0011 1000 Chapter 4 — The Processor — 12

Clocking Methodology n Combinational logic transforms data during clock cycles n n n Between clock edges Input from state elements, output to state element Longest delay determines clock period Cycle 2 1000 Cycle 1 0011 1000 Chapter 4 — The Processor — 13

n Datapath n Elements that process data and addresses in the CPU n n § 4. 3 Building a Datapath Registers, ALUs, mux’s, memories, … We will build a MIPS datapath incrementally n Refining the overview design Chapter 4 — The Processor — 14

Instruction Fetch 0 x 0104 0 x 0100 32 -bit register Add $t 1, $t 2, $t 3 Increment by 4 for next instruction Chapter 4 — The Processor — 15

R-Format Instructions n n n Read two register operands Perform arithmetic/logical operation Write register result add 01010 20 20 30 30 sub 01011 01000 50 50 1: write Chapter 4 — The Processor — 16

Load/Store Instructions n n Read register operands Calculate address using 16 -bit offset n n n Use ALU, but sign-extend offset Load: Read memory and update register Store: Write register value to memory 1: write 0 x 1010 10 00000011 11111100 11111110 00000011 1111110 50 1: read Chapter 4 — The Processor — 17

Branch Instructions n n Read register operands Compare operands n n Use ALU, subtract and check Zero output Calculate target address n n n Sign-extend displacement Shift left 2 places (word displacement) Add to PC + 4 n Already calculated by instruction fetch Chapter 4 — The Processor — 18

Branch Instructions Just re-routes wires $t 1 Beq $t 1, $t 2, 10 10 $t 2 subtract 0 20 Sign-bit wire replicated Chapter 4 — The Processor — 19

Composing the Elements n First-cut data path does an instruction in one clock cycle n n n Each datapath element can only do one function at a time Hence, we need separate instruction and data memories Use multiplexers where alternate data sources are used for different instructions Chapter 4 — The Processor — 20

R-Type/Load/Store Datapath Chapter 4 — The Processor — 21

Full Datapath Chapter 4 — The Processor — 22

Full Datapath for Add $t 1, $t 2, $t 3 0 x 0104 0 x 0100 Add $t 1, $t 2, $t 3 $t 2 $t 3 $t 1 20 50 30 30 50 Chapter 4 — The Processor — 23

Full Datapath for Add $t 1, $t 2, $t 3 0 x 0104 0 x 0100 01011 00000000 00010100 0 x 0100 000000 01011 01001 00000100000 01001 50 30 30 50 Chapter 4 — The Processor — 24

Exercise: lw $t 1, 40($t 2) ? ? ? 0 x 1100 lw $t 1, 40(t 2) ? ? ? ? Chapter 4 — The Processor — 25

Exercise: slt $t 1, $t 2, $t 3 ? ? ? 0 x 1100 slt $t 1, $t 2, $t 3 ? ? ? ? Chapter 4 — The Processor — 26

Exercise: beq $t 1, $t 2, 20 ? ? ? 0 x 1100 beq $t 1, $t 2, 20 ? ? ? ? Chapter 4 — The Processor — 27

n ALU used for n n n Load/Store: F = add Branch: F = subtract R-type: F depends on funct field ALU control Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than 1100 NOR § 4. 4 A Simple Implementation Scheme ALU Control Chapter 4 — The Processor — 28

ALU Control n Assume 2 -bit ALUOp derived from opcode n Combinational logic derives ALU control opcode ALUOp Operation funct ALU function ALU control lw 00 load word XXXXXX add 0010 sw 00 store word XXXXXX add 0010 beq 01 branch equal XXXXXX subtract 0110 R-type 10 add 100000 add 0010 subtract 100010 subtract 0110 AND 100100 AND 0000 OR 100101 OR 0001 set-on-less-than 101010 set-on-less-than 0111 Chapter 4 — The Processor — 29

The Main Control Unit n Control signals derived from instruction R-type Load/ Store Branch 0 rs rt rd shamt funct 31: 26 25: 21 20: 16 15: 11 10: 6 5: 0 35 or 43 rs rt address 31: 26 25: 21 20: 16 15: 0 4 rs rt address 31: 26 25: 21 20: 16 15: 0 opcode always read, except for load write for R -type and load sign-extend add Chapter 4 — The Processor — 30

Datapath With Control Chapter 4 — The Processor — 31

R-Type Instruction Chapter 4 — The Processor — 32

R-Type Instruction 0 x 0104 0 0 x 0100 $t 2 20 $t 3 0 x 0100 Add $t 1, $t 2, $t 3 30 $t 1 0 0 30 50 1 1 Chapter 4 — The Processor — 33

Load Instruction: lw $t 1, 40($t 2) 0 x 1100 lw $t 1, 40($t 2) Chapter 4 — The Processor — 34

Branch-on-Equal Instruction: beq $t 1, $t 2, 20 0 x 1100 beq $t 1, $t 2, 20 Chapter 4 — The Processor — 35

Implementing Jumps Jump n n address 31: 26 25: 0 Jump uses word address Update PC with concatenation of n n 2 Top 4 bits of old PC 26 -bit jump address 00 Need an extra control signal decoded from opcode Chapter 4 — The Processor — 36

Datapath With Jumps Added Chapter 4 — The Processor — 37

Determining Clock Cycle (And) 950 980 300 700 980 200 1180 600 I-Mem: 400 ps Add: 100 ps Mux: 30 ps ALU: 120 ps Regs: 200 ps D-Mem: 350 ps Control: 100 ps 1180 800 830 950 700 Chapter 4 — The Processor — 38

Determining Clock Cycle (lw) ? I-Mem: 400 ps Add: 100 ps Mux: 30 ps ALU: 120 ps Regs: 200 ps D-Mem: 350 ps Control: 100 ps ? ? ? ? ? ? Chapter 4 — The Processor — 39

Determining Clock Cycle (lw) 920 I-Mem: 400 ps Add: 100 ps Mux: 30 ps ALU: 120 ps Regs: 200 ps D-Mem: 350 ps Control: 100 ps 920 950 300 700 1300 200 1150 600 1500 800 ? 730 920 1270 700 Chapter 4 — The Processor — 40

Performance Issues n Longest delay determines clock period n n Not feasible to vary period for different instructions Violates design principle n n Critical path: load instruction Instruction memory register file ALU data memory register file Making the common case fast We will improve performance by pipelining Chapter 4 — The Processor — 41

n Pipelined laundry: overlapping execution n Parallelism improves performance n Four loads: n n § 4. 5 An Overview of Pipelining Analogy Speedup = 8/3. 5 = 2. 3 Non-stop: n Speedup = 2 n/0. 5 n + 1. 5 ≈ 4 = number of stages Chapter 4 — The Processor — 42

MIPS Pipeline n Five stages, one step per stage 1. 2. 3. 4. 5. IF: Instruction fetch from memory ID: Instruction decode & register read EX: Execute operation or calculate address MEM: Access memory operand WB: Write result back to register Chapter 4 — The Processor — 43

Pipeline Performance n Assume time for stages is n n n 100 ps for register read or write 200 ps for other stages Compare pipelined datapath with single-cycle datapath Instr fetch Register read ALU op Memory access Register write Total time lw 200 ps 100 ps 800 ps sw 200 ps 100 ps 200 ps R-format 200 ps 100 ps 200 ps beq 200 ps 100 ps 200 ps 700 ps 100 ps 600 ps 500 ps Chapter 4 — The Processor — 44

Pipeline Performance Single-cycle (Tc= 800 ps) Pipelined (Tc= 200 ps) Chapter 4 — The Processor — 45

Pipeline Speedup n If all stages are balanced n n i. e. , all take the same time Time between instructionspipelined = Time between instructionsnonpipelined Number of stages If not balanced, speedup is less Speedup due to increased throughput n Latency (time for each instruction) does not decrease Chapter 4 — The Processor — 46

Pipelining and ISA Design n MIPS ISA designed for pipelining n All instructions are 32 -bits n n n Few and regular instruction formats n n Can decode and read registers in one step Load/store addressing n n Easier to fetch and decode in one cycle c. f. x 86: 1 - to 17 -byte instructions Can calculate address in 3 rd stage, access memory in 4 th stage Alignment of memory operands n Memory access takes only one cycle Chapter 4 — The Processor — 47

Hazards n n Situations that prevent starting the next instruction in the next cycle Structure hazards n n Data hazard n n A required resource is busy Need to wait for previous instruction to complete its data read/write Control hazard n Deciding on control action depends on previous instruction Chapter 4 — The Processor — 48

Structure Hazards n n Conflict for use of a resource In MIPS pipeline with a single memory n n Load/store requires data access Instruction fetch would have to stall for that cycle n n Would cause a pipeline “bubble” Hence, pipelined datapaths require separate instruction/data memories n Or separate instruction/data caches Chapter 4 — The Processor — 49

Data Hazards n An instruction depends on completion of data access by a previous instruction n add sub $s 0, $t 1 $t 2, $s 0, $t 3 Chapter 4 — The Processor — 50

Forwarding (aka Bypassing) n Use result when it is computed n n Don’t wait for it to be stored in a register Requires extra connections in the datapath Chapter 4 — The Processor — 51

Load-Use Data Hazard n Can’t always avoid stalls by forwarding n n If value not computed when needed Can’t forward backward in time! Chapter 4 — The Processor — 52

Code Scheduling to Avoid Stalls n n Reorder code to avoid use of load result in the next instruction C code for A = B + E; C = B + F; stall lw lw add sw $t 1, $t 2, $t 3, $t 4, $t 5, 0($t 0) 4($t 0) $t 1, $t 2 12($t 0) 8($t 0) $t 1, $t 4 16($t 0) 13 cycles lw lw lw add sw $t 1, $t 2, $t 4, $t 3, $t 5, 0($t 0) 4($t 0) 8($t 0) $t 1, $t 2 12($t 0) $t 1, $t 4 16($t 0) 11 cycles Chapter 4 — The Processor — 53

Control Hazards n Branch determines flow of control n n Fetching next instruction depends on branch outcome Pipeline can’t always fetch correct instruction n n Still working on ID stage of branch In MIPS pipeline n n Need to compare registers and compute target early in the pipeline Add hardware to do it in ID stage Chapter 4 — The Processor — 54

Stall on Branch n Wait until branch outcome determined before fetching next instruction Chapter 4 — The Processor — 55

Branch Prediction n Longer pipelines can’t readily determine branch outcome early n n Predict outcome of branch n n Stall penalty becomes unacceptable Only stall if prediction is wrong In MIPS pipeline n n Can predict branches not taken Fetch instruction after branch, with no delay Chapter 4 — The Processor — 56

MIPS with Predict Not Taken Prediction correct Prediction incorrect Chapter 4 — The Processor — 57

More-Realistic Branch Prediction n Static branch prediction n n Based on typical branch behavior Example: loop and if-statement branches n n n Predict backward branches taken Predict forward branches not taken Dynamic branch prediction n Hardware measures actual branch behavior n n e. g. , record recent history of each branch Assume future behavior will continue the trend n When wrong, stall while re-fetching, and update history Chapter 4 — The Processor — 58

Pipeline Summary The BIG Picture n Pipelining improves performance by increasing instruction throughput n n n Subject to hazards n n Executes multiple instructions in parallel Each instruction has the same latency Structure, data, control Instruction set design affects complexity of pipeline implementation Chapter 4 — The Processor — 59

§ 4. 6 Pipelined Datapath and Control MIPS Pipelined Datapath MEM Right-to-left flow leads to hazards WB Chapter 4 — The Processor — 60

Pipeline registers n Need registers between stages n To hold information produced in previous cycle Chapter 4 — The Processor — 61

Pipeline Operation n Cycle-by-cycle flow of instructions through the pipelined datapath n “Single-clock-cycle” pipeline diagram n n n c. f. “multi-clock-cycle” diagram n n Shows pipeline usage in a single cycle Highlight resources used Graph of operation over time We’ll look at “single-clock-cycle” diagrams for load & store Chapter 4 — The Processor — 62

IF for Load, Store, … Chapter 4 — The Processor — 63

ID for Load, Store, … Chapter 4 — The Processor — 64

EX for Load Chapter 4 — The Processor — 65

MEM for Load Chapter 4 — The Processor — 66

WB for Load Wrong register number Chapter 4 — The Processor — 67

Corrected Datapath for Load Chapter 4 — The Processor — 68

EX for Store Chapter 4 — The Processor — 69

MEM for Store Chapter 4 — The Processor — 70

WB for Store Chapter 4 — The Processor — 71

Multi-Cycle Pipeline Diagram n Form showing resource usage Chapter 4 — The Processor — 72

Multi-Cycle Pipeline Diagram n Traditional form Chapter 4 — The Processor — 73

Single-Cycle Pipeline Diagram n State of pipeline in a given cycle Chapter 4 — The Processor — 74

Pipelined Control (Simplified) Chapter 4 — The Processor — 75

Pipelined Control n Control signals derived from instruction n As in single-cycle implementation Chapter 4 — The Processor — 76

Pipelined Control Chapter 4 — The Processor — 77

n Consider this sequence: sub and or add sw n $2, $1, $3 $12, $5 $13, $6, $2 $14, $2 $15, 100($2) We can resolve hazards with forwarding n § 4. 7 Data Hazards: Forwarding vs. Stalling Data Hazards in ALU Instructions How do we detect when to forward? Chapter 4 — The Processor — 78

Dependencies & Forwarding Chapter 4 — The Processor — 79

Detecting the Need to Forward n Pass register numbers along pipeline n n ALU operand register numbers in EX stage are given by n n e. g. , ID/EX. Register. Rs = register number for Rs sitting in ID/EX pipeline register ID/EX. Register. Rs, ID/EX. Register. Rt Data hazards when 1 a. EX/MEM. Register. Rd = ID/EX. Register. Rs 1 b. EX/MEM. Register. Rd = ID/EX. Register. Rt 2 a. MEM/WB. Register. Rd = ID/EX. Register. Rs 2 b. MEM/WB. Register. Rd = ID/EX. Register. Rt Fwd from EX/MEM pipeline reg Fwd from MEM/WB pipeline reg Chapter 4 — The Processor — 80

Detecting the Need to Forward n But only if forwarding instruction will write to a register! n n EX/MEM. Reg. Write, MEM/WB. Reg. Write And only if Rd for that instruction is not $zero n EX/MEM. Register. Rd ≠ 0, MEM/WB. Register. Rd ≠ 0 Chapter 4 — The Processor — 81

Forwarding Paths Chapter 4 — The Processor — 82

Forwarding Conditions n EX hazard n n n if (EX/MEM. Reg. Write and (EX/MEM. Register. Rd ≠ 0) and (EX/MEM. Register. Rd = ID/EX. Register. Rs)) Forward. A = 10 if (EX/MEM. Reg. Write and (EX/MEM. Register. Rd ≠ 0) and (EX/MEM. Register. Rd = ID/EX. Register. Rt)) Forward. B = 10 MEM hazard n n if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd ≠ 0) and (MEM/WB. Register. Rd = ID/EX. Register. Rs)) Forward. A = 01 if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd ≠ 0) and (MEM/WB. Register. Rd = ID/EX. Register. Rt)) Forward. B = 01 Chapter 4 — The Processor — 83

Double Data Hazard n Consider the sequence: add $1, $2 add $1, $3 add $1, $4 n Both hazards occur n n Want to use the most recent Revise MEM hazard condition n Only fwd if EX hazard condition isn’t true Chapter 4 — The Processor — 84

Revised Forwarding Condition n MEM hazard n n if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd ≠ 0) and not (EX/MEM. Reg. Write and (EX/MEM. Register. Rd ≠ 0) and (EX/MEM. Register. Rd = ID/EX. Register. Rs)) and (MEM/WB. Register. Rd = ID/EX. Register. Rs)) Forward. A = 01 if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd ≠ 0) and not (EX/MEM. Reg. Write and (EX/MEM. Register. Rd ≠ 0) and (EX/MEM. Register. Rd = ID/EX. Register. Rt)) and (MEM/WB. Register. Rd = ID/EX. Register. Rt)) Forward. B = 01 Chapter 4 — The Processor — 85

Datapath with Forwarding Chapter 4 — The Processor — 86

Load-Use Data Hazard Need to stall for one cycle Chapter 4 — The Processor — 87

Load-Use Hazard Detection n n Check when using instruction is decoded in ID stage ALU operand register numbers in ID stage are given by n n Load-use hazard when n n IF/ID. Register. Rs, IF/ID. Register. Rt ID/EX. Mem. Read and ((ID/EX. Register. Rt = IF/ID. Register. Rs) or (ID/EX. Register. Rt = IF/ID. Register. Rt)) If detected, stall and insert bubble Chapter 4 — The Processor — 88

How to Stall the Pipeline n Force control values in ID/EX register to 0 n n EX, MEM and WB do nop (no-operation) Prevent update of PC and IF/ID register n n n Using instruction is decoded again Following instruction is fetched again 1 -cycle stall allows MEM to read data for lw n Can subsequently forward to EX stage Chapter 4 — The Processor — 89

Stall/Bubble in the Pipeline Stall inserted here Chapter 4 — The Processor — 90

Stall/Bubble in the Pipeline Or, more accurately… Chapter 4 — The Processor — 91

Datapath with Hazard Detection Chapter 4 — The Processor — 92

Stalls and Performance The BIG Picture n Stalls reduce performance n n But are required to get correct results Compiler can arrange code to avoid hazards and stalls n Requires knowledge of the pipeline structure Chapter 4 — The Processor — 93

n If branch outcome determined in MEM § 4. 8 Control Hazards Branch Hazards Flush these instructions (Set control values to 0) PC Chapter 4 — The Processor — 94

Reducing Branch Delay n Move hardware to determine outcome to ID stage n n n Target address adder Register comparator Example: branch taken 36: 40: 44: 48: 52: 56: 72: sub beq and or add slt. . . lw $10, $12, $13, $14, $15, $4, $3, $2, $4, $6, $8 7 $5 $6 $2 $7 $4, 50($7) Chapter 4 — The Processor — 95

Example: Branch Taken Chapter 4 — The Processor — 96

Example: Branch Taken Chapter 4 — The Processor — 97

Data Hazards for Branches n If a comparison register is a destination of 2 nd or 3 rd preceding ALU instruction add $1, $2, $3 IF add $4, $5, $6 … beq $1, $4, target n ID EX MEM WB IF ID EX MEM WB Can resolve using forwarding Chapter 4 — The Processor — 98

Data Hazards for Branches n If a comparison register is a destination of preceding ALU instruction or 2 nd preceding load instruction n lw Need 1 stall cycle $1, addr IF add $4, $5, $6 beq stalled beq $1, $4, target ID EX MEM WB IF ID ID EX MEM WB Chapter 4 — The Processor — 99

Data Hazards for Branches n If a comparison register is a destination of immediately preceding load instruction n lw Need 2 stall cycles $1, addr IF beq stalled beq $1, $0, target ID EX IF ID MEM WB ID ID EX MEM WB Chapter 4 — The Processor — 100

Dynamic Branch Prediction n n In deeper and superscalar pipelines, branch penalty is more significant Use dynamic prediction n n Branch prediction buffer (aka branch history table) Indexed by recent branch instruction addresses Stores outcome (taken/not taken) To execute a branch n n n Check table, expect the same outcome Start fetching from fall-through or target If wrong, flush pipeline and flip prediction Chapter 4 — The Processor — 101

1 -Bit Predictor: Shortcoming n Inner loop branches mispredicted twice! outer: … … inner: … … beq …, …, inner … beq …, …, outer n n Mispredict as taken on last iteration of inner loop Then mispredict as not taken on first iteration of inner loop next time around Chapter 4 — The Processor — 102

2 -Bit Predictor n Only change prediction on two successive mispredictions Chapter 4 — The Processor — 103

Calculating the Branch Target n Even with predictor, still need to calculate the target address n n 1 -cycle penalty for a taken branch Branch target buffer n n Cache of target addresses Indexed by PC when instruction fetched n If hit and instruction is branch predicted taken, can fetch target immediately Chapter 4 — The Processor — 104

n “Unexpected” events requiring change in flow of control n n Different ISAs use the terms differently Exception n Arises within the CPU n n e. g. , undefined opcode, overflow, syscall, … Interrupt n n § 4. 9 Exceptions and Interrupts From an external I/O controller Dealing with them without sacrificing performance is hard Chapter 4 — The Processor — 105

Handling Exceptions n n In MIPS, exceptions managed by a System Control Coprocessor (CP 0) Save PC of offending (or interrupted) instruction n n In MIPS: Exception Program Counter (EPC) Save indication of the problem n n In MIPS: Cause register We’ll assume 1 -bit n n 0 for undefined opcode, 1 for overflow Jump to handler at 8000 00180 Chapter 4 — The Processor — 106

An Alternate Mechanism n Vectored Interrupts n n Example: n n Handler address determined by the cause Undefined opcode: Overflow: …: C 0000 C 000 0020 C 000 0040 Instructions either n n Deal with the interrupt, or Jump to real handler Chapter 4 — The Processor — 107

Handler Actions n n n Read cause, and transfer to relevant handler Determine action required If restartable n n n Take corrective action use EPC to return to program Otherwise n n Terminate program Report error using EPC, cause, … Chapter 4 — The Processor — 108

Exceptions in a Pipeline n n Another form of control hazard Consider overflow on add in EX stage add $1, $2, $1 n Prevent $1 from being clobbered n Complete previous instructions n Flush add and subsequent instructions n Set Cause and EPC register values n Transfer control to handler n Similar to mispredicted branch n Use much of the same hardware Chapter 4 — The Processor — 109

Pipeline with Exceptions Chapter 4 — The Processor — 110

Exception Properties n Restartable exceptions n n Pipeline can flush the instruction Handler executes, then returns to the instruction n n Refetched and executed from scratch PC saved in EPC register n n Identifies causing instruction Actually PC + 4 is saved n Handler must adjust Chapter 4 — The Processor — 111

Exception Example n Exception on add in 40 44 48 4 C 50 54 … n sub and or add slt lw $11, $12, $13, $15, $16, $2, $4 $2, $5 $2, $6 $2, $1 $6, $7 50($7) sw sw $25, 1000($0) $26, 1004($0) Handler 80000180 80000184 … Chapter 4 — The Processor — 112

Exception Example Chapter 4 — The Processor — 113

Exception Example Chapter 4 — The Processor — 114

Multiple Exceptions n Pipelining overlaps multiple instructions n n Simple approach: deal with exception from earliest instruction n Could have multiple exceptions at once Flush subsequent instructions “Precise” exceptions In complex pipelines n n n Multiple instructions issued per cycle Out-of-order completion Maintaining precise exceptions is difficult! Chapter 4 — The Processor — 115

Imprecise Exceptions n Just stop pipeline and save state n n Including exception cause(s) Let the handler work out n n Which instruction(s) had exceptions Which to complete or flush n n n May require “manual” completion Simplifies hardware, but more complex handler software Not feasible for complex multiple-issue out-of-order pipelines Chapter 4 — The Processor — 116

n n Pipelining: executing multiple instructions in parallel To increase ILP n Deeper pipeline n n Less work per stage shorter clock cycle Multiple issue n n Replicate pipeline stages multiple pipelines Start multiple instructions per clock cycle CPI < 1, so use Instructions Per Cycle (IPC) E. g. , 4 GHz 4 -way multiple-issue n n 16 BIPS, peak CPI = 0. 25, peak IPC = 4 But dependencies reduce this in practice § 4. 10 Parallelism and Advanced Instruction Level Parallelism Instruction-Level Parallelism (ILP) Chapter 4 — The Processor — 117

Multiple Issue n Static multiple issue n n Compiler groups instructions to be issued together Packages them into “issue slots” Compiler detects and avoids hazards Dynamic multiple issue n n n CPU examines instruction stream and chooses instructions to issue each cycle Compiler can help by reordering instructions CPU resolves hazards using advanced techniques at runtime Chapter 4 — The Processor — 118

Speculation n “Guess” what to do with an instruction n n Start operation as soon as possible Check whether guess was right n n If so, complete the operation If not, roll-back and do the right thing Common to static and dynamic multiple issue Examples n Speculate on branch outcome n n Roll back if path taken is different Speculate on load n Roll back if location is updated Chapter 4 — The Processor — 119

Compiler/Hardware Speculation n Compiler can reorder instructions n n n e. g. , move load before branch Can include “fix-up” instructions to recover from incorrect guess Hardware can look ahead for instructions to execute n n Buffer results until it determines they are actually needed Flush buffers on incorrect speculation Chapter 4 — The Processor — 120

Speculation and Exceptions n What if exception occurs on a speculatively executed instruction? n n Static speculation n n e. g. , speculative load before null-pointer check Can add ISA support for deferring exceptions Dynamic speculation n Can buffer exceptions until instruction completion (which may not occur) Chapter 4 — The Processor — 121

Static Multiple Issue n Compiler groups instructions into “issue packets” n n n Group of instructions that can be issued on a single cycle Determined by pipeline resources required Think of an issue packet as a very long instruction n n Specifies multiple concurrent operations Very Long Instruction Word (VLIW) Chapter 4 — The Processor — 122

Scheduling Static Multiple Issue n Compiler must remove some/all hazards n n n Reorder instructions into issue packets No dependencies with a packet Possibly some dependencies between packets n n Varies between ISAs; compiler must know! Pad with nop if necessary Chapter 4 — The Processor — 123

MIPS with Static Dual Issue n Two-issue packets n n n One ALU/branch instruction One load/store instruction 64 -bit aligned n n ALU/branch, then load/store Pad an unused instruction with nop Address Instruction type Pipeline Stages n ALU/branch IF ID EX MEM WB n+4 Load/store IF ID EX MEM WB n+8 ALU/branch IF ID EX MEM WB n + 12 Load/store IF ID EX MEM WB n + 16 ALU/branch IF ID EX MEM WB n + 20 Load/store IF ID EX MEM WB Chapter 4 — The Processor — 124

MIPS with Static Dual Issue Chapter 4 — The Processor — 125

Hazards in the Dual-Issue MIPS n n More instructions executing in parallel EX data hazard n n Forwarding avoided stalls with single-issue Now can’t use ALU result in load/store in same packet n n n Load-use hazard n n add $t 0, $s 1 load $s 2, 0($t 0) Split into two packets, effectively a stall Still one cycle use latency, but now two instructions More aggressive scheduling required Chapter 4 — The Processor — 126

Scheduling Example n Schedule this for dual-issue MIPS Loop: lw addu sw addi bne Loop: n $t 0, $s 1, 0($s 1) $t 0, $s 2 0($s 1) $s 1, – 4 $zero, Loop # # # $t 0=array element add scalar in $s 2 store result decrement pointer branch $s 1!=0 ALU/branch Load/store cycle nop lw 1 addi $s 1, – 4 nop 2 addu $t 0, $s 2 nop 3 bne sw $s 1, $zero, Loop $t 0, 0($s 1) $t 0, 4($s 1) 4 IPC = 5/4 = 1. 25 (c. f. peak IPC = 2) Chapter 4 — The Processor — 127

Loop Unrolling n Replicate loop body to expose more parallelism n n Reduces loop-control overhead Use different registers per replication n n Called “register renaming” Avoid loop-carried “anti-dependencies” n n Store followed by a load of the same register Aka “name dependence” n Reuse of a register name Chapter 4 — The Processor — 128

Loop Unrolling Example Loop: ALU/branch Load/store cycle addi $s 1, – 16 lw $t 0, 0($s 1) 1 nop lw $t 1, 12($s 1) 2 addu $t 0, $s 2 lw $t 2, 8($s 1) 3 addu $t 1, $s 2 lw $t 3, 4($s 1) 4 addu $t 2, $s 2 sw $t 0, 16($s 1) 5 addu $t 3, $t 4, $s 2 sw $t 1, 12($s 1) 6 nop sw $t 2, 8($s 1) 7 sw $t 3, 4($s 1) 8 bne n $s 1, $zero, Loop IPC = 14/8 = 1. 75 n Closer to 2, but at cost of registers and code size Chapter 4 — The Processor — 129

Dynamic Multiple Issue n n “Superscalar” processors CPU decides whether to issue 0, 1, 2, … each cycle n n Avoiding structural and data hazards Avoids the need for compiler scheduling n n Though it may still help Code semantics ensured by the CPU Chapter 4 — The Processor — 130

Dynamic Pipeline Scheduling n Allow the CPU to execute instructions out of order to avoid stalls n n But commit result to registers in order Example n lw $t 0, 20($s 2) addu $t 1, $t 0, $t 2 sub $s 4, $t 3 slti $t 5, $s 4, 20 Can start sub while addu is waiting for lw Chapter 4 — The Processor — 131

Dynamically Scheduled CPU Preserves dependencies Hold pending operands Results also sent to any waiting reservation stations Reorders buffer for register writes Can supply operands for issued instructions Chapter 4 — The Processor — 132

Register Renaming n n Reservation stations and reorder buffer effectively provide register renaming On instruction issue to reservation station n If operand is available in register file or reorder buffer n n n Copied to reservation station No longer required in the register; can be overwritten If operand is not yet available n n It will be provided to the reservation station by a function unit Register update may not be required Chapter 4 — The Processor — 133

Speculation n Predict branch and continue issuing n n Don’t commit until branch outcome determined Load speculation n Avoid load and cache miss delay n n n Predict the effective address Predict loaded value Load before completing outstanding stores Bypass stored values to load unit Don’t commit load until speculation cleared Chapter 4 — The Processor — 134

Why Do Dynamic Scheduling? n n Why not just let the compiler schedule code? Not all stalls are predicable n n Can’t always schedule around branches n n e. g. , cache misses Branch outcome is dynamically determined Different implementations of an ISA have different latencies and hazards Chapter 4 — The Processor — 135

Does Multiple Issue Work? The BIG Picture n n n Yes, but not as much as we’d like Programs have real dependencies that limit ILP Some dependencies are hard to eliminate n n Some parallelism is hard to expose n n Limited window size during instruction issue Memory delays and limited bandwidth n n e. g. , pointer aliasing Hard to keep pipelines full Speculation can help if done well Chapter 4 — The Processor — 136

Power Efficiency n n Complexity of dynamic scheduling and speculations requires power Multiple simpler cores may be better Microprocessor Year Clock Rate Pipeline Stages Issue width Out-of-order/ Speculation Cores Power i 486 1989 25 MHz 5 1 No 1 5 W Pentium 1993 66 MHz 5 2 No 1 10 W Pentium Pro 1997 200 MHz 10 3 Yes 1 29 W P 4 Willamette 2001 2000 MHz 22 3 Yes 1 75 W P 4 Prescott 2004 3600 MHz 31 3 Yes 1 103 W Core 2006 2930 MHz 14 4 Yes 2 75 W Ultra. Sparc III 2003 1950 MHz 14 4 No 1 90 W Ultra. Sparc T 1 2005 1200 MHz 6 1 No 8 70 W Chapter 4 — The Processor — 137

72 physical registers § 4. 11 Real Stuff: The AMD Opteron X 4 (Barcelona) Pipeline The Opteron X 4 Microarchitecture Chapter 4 — The Processor — 138

The Opteron X 4 Pipeline Flow n For integer operations n n n FP is 5 stages longer Up to 106 RISC-ops in progress Bottlenecks n n n Complex instructions with long dependencies Branch mispredictions Memory access delays Chapter 4 — The Processor — 139

§ 4. 13 Fallacies and Pitfalls Fallacies n Pipelining is easy (!) n n The basic idea is easy The devil is in the details n n e. g. , detecting data hazards Pipelining is independent of technology n n n So why haven’t we always done pipelining? More transistors make more advanced techniques feasible Pipeline-related ISA design needs to take account of technology trends n e. g. , predicated instructions Chapter 4 — The Processor — 140

Pitfalls n Poor ISA design can make pipelining harder n e. g. , complex instruction sets (VAX, IA-32) n n n e. g. , complex addressing modes n n Significant overhead to make pipelining work IA-32 micro-op approach Register update side effects, memory indirection e. g. , delayed branches n Advanced pipelines have long delay slots Chapter 4 — The Processor — 141

n n n ISA influences design of datapath and control Datapath and control influence design of ISA Pipelining improves instruction throughput using parallelism n n § 4. 14 Concluding Remarks More instructions completed per second Latency for each instruction not reduced Hazards: structural, data, control Multiple issue and dynamic scheduling (ILP) n n Dependencies limit achievable parallelism Complexity leads to the power wall Chapter 4 — The Processor — 142