Fotios Vartziotis VLSI Design VLSI testing Hardware Security

Fotios Vartziotis • VLSI Design • VLSI testing • Hardware Security December 12, 2021 Θεματικές Ενότητες 2

• Simple Cycle • Pipelined Fotios Vartziotis • RTL Design • MIPS R 2000 RISC Microprocessor December 12, 2021 VLSI Design 3

Fotios Vartziotis December 12, 2021 MIPS Components 4

VLSI Testing Scan Design Built-In Self-Test Fotios Vartziotis December 12, 2021 • Df. T 5

• Each embedded core is an independent testable unit Fotios Vartziotis • Modular Testing December 12, 2021 Testing at So. C Level 6

cost considerations Challenges: Small number of ATE channels, TAM resources are shared to multiple cores Fotios Vartziotis The Test Access Mechanism (TAM) is designed with December 12, 2021 TAM Configurations 7

Fotios Vartziotis • Goal: To minimize test application time December 12, 2021 Test Scheduling 8 Source: S. Samii, ITC, 2006

• • • Power Time Faults Electro-Magnetic radiations Sound Scan Chains Fotios Vartziotis • Side Channel Attacks using: December 12, 2021 Hardware Security • Countermeasures 9

Example: Power Analysis Attack Fotios Vartziotis Trace of Current drawn - RSA Secret Key Computation December 12, 2021 Idea: During switching CMOS gates draw spiked current Only Squaring and multiplication Reported Results : Every Smartcard in the market BROKEN 10