FLIPFLOPS 1 SR latch n Crosscoupled NOR gates

FLIPFLOPS 1

SR latch n Cross-coupled NOR gates ¡ R S Can set (S=1, R=0) or reset (R=1, S=0) the output Q Q' Reset R Q Set S Q S 0 0 1 1 R 0 1 Q hold 0 1 disallow 2

SR latch behavior R Q S Q' Reset Hold Set S 0 0 1 1 R 0 1 Q hold 0 1 disallow Reset Set 100 Race R S Q Q' 3

SR latch is glitch sensitive n Static 0 glitches can set/reset latch ¡ ¡ 0 0 Glitch on S input sets latch Glitch on R input resets latch R Q S Q' 4

State diagrams n How do we characterize logic circuits? ¡ ¡ n First draw the states ¡ n Combinational circuits: Truth tables Sequential circuits: State diagrams States Unique circuit configurations Second draw the transitions between states ¡ Transitions Changes in state caused by inputs 5

Example: SR latch SR=10 R Q Q Q' 0 1 Q' S S 0 0 1 1 SR=00 SR=01 R 0 1 Q hold 0 1 disallow Q Q' 1 0 SR=10 SR=01 SR=11 SR=01 possible oscillation between states 00 and 11 (when SR=00) Q Q' 0 0 SR=00 SR=11 SR=10 SR=00 Q Q' 1 1 6

Observed SR latch behavior n The 1– 1 state is transitory ¡ ¡ ¡ Either R or S “gets ahead” Latch settles to 0– 1 or 1– 0 state ambiguously Race condition non-deterministic transition n Disallow (R, S) = (1, 1) SR=10 SR=01 Q Q' 0 1 Q Q' 1 0 SR=00 SR=10 SR=01 7

D ("data") latch n Output depends on clock ¡ ¡ Input Clock high: Input passes to output Clock low: Latch holds its output D Q Q CLK D Qlatch 8

Making a D latch D CLK D R Q S Q 9

D flip-flop n Input sampled at clock edge ¡ ¡ n Input Rising edge: Input passes to output Otherwise: Flip-flop holds its output D Q Q CLK Flip-flops can be rising-edge triggered or falling-edge triggered CLK D Qff 10

Master-slave D-type flip-flop Master D latch Input D Q X Slave D latch D Q Output CLK n How to make into negative edgetriggered D-type flip-flop? 11

Latches versus flip-flops D Q CLK Q D CLK D Q Q CLK Qff Qlatch behavior is the same unless input changes while the clock is high 12

Terminology and notation Rising-edge triggered D flip-flop Input D Q Output Positive D latch Input D Q Output CLK Falling-edge triggered D flip-flop Negative D latch Input D CLK Q Output 13

How to make a D flip-flop? n Edge triggering is difficult ¡ ¡ ¡ Label the internal nodes Draw a timing diagram Start with Clk=1 W X Q Clk Q’ Y D Z 14

How to make a D flip flop? Falling edge-triggered flip-flop If Clk=1 then X=Y=0 and SR latch block holds previous values of Q, Q’, also Z=D’ and W=Z’=D. W X Q When Clk 0 then Y (set for SR latch block) becomes Z’=D and X (reset for SR latch Clk block) becomes W’=D’ so Q becomes D. Q’ Y While Clk=0, if D switches then Z becomes 0 (because inputs to Z are D and D') and X and D W hold their previous values and Y=X’=D as before. Z 15

T ("toggle") flip-flop n Output toggles when input is asserted ¡ ¡ If T=1, then Q Q' when CLK If T=0, then Q Q when CLK Input T Q > CLK Q Input(t) 0 0 1 1 Q(t) 0 1 Q(t + t) 0 1 1 0 16