FlipFlop Flipflops Objectives Upon completion of this chapter
Flip-Flop
Flip-flops Objectives Upon completion of this chapter, you will be able to : Ø Construct and analyze the operation of a latch flip-flop made from NAND or NOR gates Ø Identify and understand the operation of RS, JK, D, T flipflops Ø Understand edge-triggered flip-flops Ø Describe the difference asynchronous systems between synchronous and
Introduction Ø Flip-flop is digital circuit which functions as a memory element used in the digital system. Ø Flip-Flop is made up of an assembly of logic gates. Even though a logic gate, by itself, has no storage capability. Ø Flip-Flop is also known as latch and bi-stable multi-vibrator.
General Flip-flop Symbol The symbol shows two outputs, labeled Q and Q, that are the inverse of each other The FF can has one or more inputs. These inputs are used to cause the FF to switch back and forth between its possible output states Q outputs FF inputs Q
General Flip-flop Symbol Flip-Flop has two allowed output states. SET state : where Q = 1 and Q = 0. RESET state : where Q = 0 and Q = 1. Q outputs FF inputs Q Thus, flip-flop is also known as bi-stable multi-vibrator or latch.
Various type of Flip-Flops R S Q J Q Q K Q RS JK Tutorial D Q Clk > >T Q D T Q Q
RS Flip-Flops The most basic flip-flop is RS flip-flop. S The inputs are labeled as SET ( S ) and RESET ( R ). The RS flip-flop can be constructed from logic gates. inputs Q outputs FF R Q
RS Flip-Flops NAND gate FF NAND-1 NAND gate FF is an active low FF. S 0 1 Q A logic 0 activates set S i. e. S = 0 Q = 1 To reset the FF, apply a logic 0 to R i. e. R = 0 Q = 1 R Q 0 1 NAND-2 Click TO Continue
RS Flip-Flops NAND gate FF NAND-1 Truth table for NAND gate RS FF S R 0 0 1 1 0 Prohibited state Set state, Q =1 1 0 0 1 Reset state, Q =1 1 Unchanged / Hold 1 Q 1 0 Q S 10 01 Remarks R 01 01 NAND-2 Click TO Continue Q Q
RS Flip-Flops NAND gate FF S inputs Block logic symbol for RS FF using NAND gate can be or Fig B. as in Fig A outputs FF R Q S Q inputs outputs FF R Click TO Continue Q Q Fig A Fig B
RS Flip-Flops NAND gate FF S Q FF Timing diagrams R Q S At time : - R Q T 0 Click TO Continue T 1 T 2 T 3 T 4 T 0 : - FF is at reset state; i. e. Q=0. T 1 : - reset signal will reset the FF. T 2 : - set signal will set the FF. T 3 : - set signal will set the FF. T 4 : - reset signal will reset the FF.
RS Flip-Flops NOR gate FF The two NOR gates are cross coupled so that the output of NOR-1 is connected to one of the inputs of NOR-2, and vice versa. NOR -1 S Q R Q NOR -2
RSNORFlip-Flops gate FF NOR gate FF is an active HIGH FF. NOR -1 S Q R Q A logic 1 activates set S i. e. S = 1 Q = 1 To reset the FF, apply a logic 1 to R i. e. R = 1 Q = 1 Click TO Continue NOR -2
RSNORFlip-Flops gate FF NAND-1 Truth table for NOR gate RS FF. S R 1 1 1 0 Prohibited state Set state, Q =1 0 1 Reset state, Q =1 1 Unchanged / Hold 0 Q 0 0 Q S 01 01 Remarks R 0101 1101 NAND-2 Click TO Continue Q Q
RS Flip-Flops NOR gate FF Block logic symbol for RS FF using NOR gate S inputs Q outputs FF R Q
RSNORFlip-Flops gate FF S Q FF Timing diagrams R Q S At time : - R Q T 0 Click TO Continue T 1 T 2 T 3 T 4 T 0 : - FF is at reset state; i. e. Q=0. T 1 : - set signal will set the FF. T 2 : - reset signal will reset the FF. T 3 : - reset signal will reset the FF. T 4 : - set signal will set the FF.
RS Flip-Flops Triggering of FF Clock pulses signal Flip-flop operates without clock input is called asynchronously. But most digital systems operate synchronously, that is operate in step with a clock signal. Flip-flop are mostly triggered by clock pulses. Click TO Continue
RS Flip-Flops Triggering of FF Clock pulses signal Flip-flop may be positive edge triggered or negative edge triggered. A positive edge-triggered flip-flop transfer data from the input to the output on the leading edge of the clock pulse. A negative edge-triggered flip-flop transfer data from the input to the output on the falling edge of the clock pulse. Click TO Continue
RS Flip-Flops Symbol of edge triggered flip-flop Positive edge triggered S Q Clk R Negative edge triggered S Q Clk Q R Q
RS Flip-Flops Logic circuit of edge triggered FF Positive edge triggered S Q Clk R S Q Clk Q R Q
JK Flip-Flops The J and K inputs are the data inputs, and clock input transfers data from inputs of the flip-flop to the outputs in the same ways as RS flipflop. The advantage of JK flip-flop is that it does not have the problem of a prohibited input combinations found in RS flip-flop. J Q CLK K Q Symbol of positive edge-triggered JK FF
JK Flip-Flops Truth table Symbol of positive edge-triggered JK FF J Q CLK K Toggle mode means when both JK are left high the FF will change states for each clock pulse. Q
JK Flip-Flops = Q remain and 1 Q to 1 J=1, K=1, Clk J=1, =Clk toggles to J=0, =Qand at toggles 0 J=0, K=1, Clk =K=0, and. K=1, = Clk 0 Qand All inputs are 0, and Q = 1 J K J Clk K Q CLK Q Q Waveform diagram for a JK flip-flop Click TO Continue
JK Flip-Flops For the clocked flip-flops , the J, K, R, and S inputs have been referred to as control inputs. These inputs are called synchronous input, because their effect on the FF output is synchronized with the CLK input. J Q CLK K Q
JK Flip-Flops Asynchronous inputs operate independently of the synchronous inputs and clock input. These inputs can be used to set the FF to the 1 state or clear the FF to the 0 state at any time, regardless of the conditions at the other inputs. J PR Q CLK K CLR Q
JK Flip-Flops Asynchronous inputs Figure show J K FF has two asynchronous inputs PR and CLR. These are active-Low inputs as indicated by the bubbles on the FF symbol. When PR = CLR=1, the asynchronous inputs are inactive. J PR Q CLK K CLR Q
JK Flip-Flops Asynchronous inputs When PR = CLR = 1, the asynchronous inputs are inactive. PR = 0, and CLR = 1, Q = 1 CLR = 0 and PR = 1, Q = 0 PR = CLR = 0, this condition should not be used ( prohibited ) , as it can result in an ambiguous response. J PR Q CLK K CLR Q
D Flip-Flops D S Q R Q J Q K Q The D flip-flop is also called Delay or Data flip-flop. The D flip-flop has only one input. It can be easily implemented from the RS or JK inputs as shown. D
DEdge-triggered Flip-Flops D FF Truth table D Clk X 0 Q Q CLK Q no change 0 0 1 1 “ X ” indicates Q follows D on the“don’t rising care” edge of the clock pulse. Click TO Continue D
D Flip-Flops D=Clk =and 1, =Clk and D =1, DClk = 0, D=Clk = 0, Qand ==1 Qand = 0 Q = 1 Initially Q = 1 D Q CLK Q D Clk Q Waveform diagram for a D flip-flop Click TO Continue
DLevel-triggered Flip-Flops D FF Truth table D EN Q X 0 0 1 1 1 D Q EN Q no change Q follows D when the FF is enabled; i. e. when EN = 1
D Flip-Flops D =0, = 1 Q=and D Q 0, 1=EN 0 and D =1, EN 1 D and Q 0== EN =0 1=and Q =Q 1 = 1 D =1, EN = EN 0=and =1, “Latched” “Transparent” Both D and EN inputs are 0, and Q = 0 D Q EN Q D EN Q Waveform diagram for a D flip-flop Click TO Continue
T Flip-Flops The T flip-flop is also called toggle flip-flop. J It can be easily implemented by tying the JK inputs of the JK FF to high as shown. K Q J Q Q T High T CLK K Q
TTruth Flip-Flops table Qn Clk Q Qn+1 0 0 1 1 0 1 T Q
T Flip-Flops Wave format T input Q T Q Wave format Q output fo = 1/2 fin fo : Output frequency at Q fin : Input frequency at T
Q 1 When both RS inputs are at logic ‘ 0’, the output Q of the flip-flop is at A) Set state. B) Reset state. S Q FF C) Hold state. D) Prohibited state. R Q
Q 2 The flip-flop shown can be constructed by using A) AND gates B) OR gates S Q FF C) NAND gates D) NOR gates R Q
Q 3 The following symbol shows A) An active high RS Flip-flop. B) An active low RS Flip-flop. C) An positive edge-trigger active low RS Flip-flop. D) An negative edge-trigger active low RS Flip-flop. S Q FF R Q
Q 4 A negative-edge-triggered flip-flop transfers data from input to output on the A) falling edge of the clock pulse B) leading edge of the clock pulse C) positive level of the clock pulse. D) zero level of the clock pulse.
Q 5 JK flip-flop does not result in A) set state B) hold state C) toggle state D) prohibited state
Q 6 When both JK inputs of the flip-flop are at logic 1, the clock pulse will cause the flip-flop to A) reset the Q output. B) set the Q output. C) hold the Q output. D) toggle the Q output to the next logic level.
Q 7 Which of the following sequence will reset the flip-flop? A) J=K=1, PR=CLR=1, and CLK = B) J=K=0, PR=CLR=1, and CLK= C) J, K, and CLK = X, where PR = 1 and CLR = 0. D) J, K, and CLk = X, where PR = 0 and CLR =1. J PR Q CLK K CLR Q
Q 8 Which of the following JK flip-flop’s mode is not an asynchronous operation? A) Set B) Clear C) Toggle D) Hold
Q 9 Refer to the figure shown; a clocked RS flip-flop had been converted to A) D flip-flop B) D latch C) T flip-flop D) JK flip-flop S Q CLK R Q
Q 10 Refer to the figure shown; for CLK frequency = 20 k. Hz the output frequency is A) 0 Hz B) 10 k. Hz D Q C) 20 k. Hz CLK Q D) 40 k. Hz
Wrong ! Q 1 When both RS inputs are at logic ‘ 0’, the output Q of the flip-flop is at A) Set state. B) Reset state. C) Hold state. D) Prohibited state. S Output Remain unchanged. Q FF R Q
Solution Q 1 When both RS inputs are at logic ‘ 0’, the output Q of the flip-flop is at A) Set state. S B) Reset state. Q FF C) unchanged state. D) prohibited state. NOR gate FF would not response to logic ‘ 0’ R Q
Q 2 Wrong ! The flip-flop shown can be constructed by using A) AND gates S B) OR gates C) NAND gates D) NOR gates Hints! Look for active low gates. Q FF R Q
Solution Q 2 The flip-flop shown can be constructed by using A) AND gates S B) OR gates Q FF C) NAND gates D) NOR gates NAND gate FF is an active low FF. R Q
Q 3 Wrong ! The following symbol shows A) An active high RS Flipflop B) An active low RS Flip-flop. C) An positive edge-trigger active low RS Flip-flop. D) An negative edge-trigger active low RS Flip-flop. S Q FF R Q Hints, Its an edge-triggered FF
Q 3 Wrong ! The following symbol shows A) An active high RS Flipflop B) An active low RS Flip-flop. C) An positive edge-trigger active low RS Flip-flop. D) An negative edge-trigger active low RS Flip-flop. S Q FF R Hints, Bubble represents negative ! Q
Solution Q 3 The following symbol shows A) An active high RS Flipflop S B) An active low RS Flip-flop. FF C) An positive edge-trigger active low RS Flip-flop. D) An negative edge-trigger active low RS Flip-flop. Q R A bubble at the clock input represent an negative edge-trigger FF. Q
Solution Q 4 A negative-edge-triggered flip-flop transfers data from input to output on the A) falling edge of the clock pulse B) leading edge of the clock pulse C) positive level of the clock pulse. D) zero level of the clock pulse. Negative edge-trigger also referred to falling edgetrigger FF.
Solution Q 5 JK flip-flop does not result in A) set state B) hold state C) toggle state D) prohibited state Prohibited state only happened in RS FF
Wrong ! Q 6 When both JK inputs of the flip-flop are at logic 1, the clock pulse will cause the flip-flop to A) reset the Q output. When J=0 , K=1 Q output will be reset. B) set the Q output. C) hold the Q output. D) toggle the Q output to the next logic level.
Wrong ! Q 6 When both JK inputs of the flip-flop are at logic 1, the clock pulse will cause the flip-flop to A) reset the Q output. B) set the Q output. When J=1 , K=0 Q output will be set. C) hold the Q output. D) toggle the Q output to the next logic level.
Wrong ! Q 6 When both JK inputs of the flip-flop are at logic 1, the clock pulse will cause the flip-flop to A) reset the Q output. B) set the Q output. C) hold the Q output. When J=K=0 Q output will be hold. D) toggle the Q output to the next logic level.
Solution Q 6 When both JK inputs of the flip-flop are at logic 1, the clock pulse will cause the flip-flop to A) reset the Q output. B) set the Q output. C) hold the Q output. When both JK FF inputs are at logic 1, the FF is said to be operated in toggle state. D) toggle the Q output to the next logic level.
Q 7 Wrong ! Which of the following sequence will reset the flip-flop? A) J=K=1, PR=CLR=1, and CLK = J B) J=K=0, PR=CLR=1, and CLK= C) J, K, and CLK = X, where PR = 1 and CLR = 0. D) J, K, and CLk = X, where PR = 0 and CLR =1. Hints! PR and CLR are asynchronous inputs. PR Q CLK K CLR Q
Q 7 Wrong ! Which of the following sequence will reset the flip-flop? A) J=K=1, PR=CLR=1, and CLK = J B) J=K=0, PR=CLR=1, and CLK= C) J, K, and CLK = X, where PR = 1 and CLR = 0. D) J, K, and CLk = X, where PR = 0 and CLR =1. Good try! Take notes of the bubble. PR Q CLK K CLR Q
Solution Q 7 Which of the following sequence will reset the flip-flop? A) J=K=1, PR=CLR=1, and CLK = B) J=K=0, PR=CLR=1, and CLK= C) J, K, and CLK = X, where PR = 1 and CLR = 0. J PR Q CLK K CLR D) J, K, and CLk = X, where PR = 0 and CLR =1. PR and CLR are asynchronous inputs, CLR=0 will reset the FF. Q
Q 8 Which of the following JK flip-flop’s mode is not an asynchronous operation? A) Set B) Clear C) Toggle D) Hold Toggle operation only took place when the Ff is triggered.
Q 9 Refer to the figure shown; a clocked RS flip-flop had been converted to A) D flip-flop B) D latch C) T flip-flop D) JK flip-flop S By connecting an inverter between the RS inputs of the FF, a D FF is formed. Q CLK R Q
Q 10 Refer to the figure shown; for CLK frequency = 20 k. Hz the output frequency is A) 0 Hz B) 10 k. Hz C) 20 k. Hz D) 40 k. Hz D FF was wired as an frequency divider cct. , the output frequency = ½ clock frequency. D Q CLK Q
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