First Wafer Results from Aptasic Vladimir Zivkovic NIKHEF

First Wafer Results from Aptasic Vladimir Zivkovic NIKHEF FE-I 4 testing meeting Amsterdam, January 9 -th 2012

Test Development for Wafer Test in Industrial environment • Test patterns pre-verified at CERN on 4 boards with wirebonded chips on Credence Sapphire platform, • Aptasic created the probe card for wafer test for their Credence Diamond Platform, • One of the CERN boards with golden device verified at Aptasic environment prior to the wafer test (with hardware adapter), • Wafer test performed at Aptasic during the last week of 2011. 1 probed wafer : V 3 ABA 5 H 3 virgin wafers: V 5 AKGRH, VCAQMBH, V 0 AK 42 H 09/01/2012 2

Test Sequence and the distribution chart • • Continuity test (pin connectivity, ESD protection diodes) Power Supply Test Scan Test (using the Df. T with scan chains) in EOCHL, DOB, CMD IDDQ Test (using the Df. T with scan chains) in EOCHL, DOB 16/11/2010 3

Wafer Map V 3 ABA 5 H • Not as bad as it looks like : – Power supply test limits might have been too tight (when the current is measured at 20. 001 m. A, the chip is deemed as failed) – The same continuity test – IDDQ test may have produced a few outliers (see following slides) – Scan test (in red) are the chips with fault 16/11/2010 4

Individual Test result distribution results – an example : IDDQ EOCHL Test 16/11/2010 5

Datalog 16/11/2010 6

Datalog (II) 16/11/2010 7

Datalog (III) 16/11/2010 8

Wafer Map Comparison Chips 12, 30, 54, 58, 60 were the test escapes in Bonn Chips 9, 16, 17, 26, 27, 38 escaped the test at Aptasic Other (parametric) mismatches require further analysis 16/11/2010 9

Test Results from the other wafers 16/11/2010 10