First thought on the TELL 40 FPGA architecture

First thought on the TELL 40 FPGA architecture NB: slides with power-point animation 1. Consult some studies • • from Guido Haefeli, Lausanne from Jean-Pierre Cachemiche, Marseille from Xavier Gremaud, Lausanne from Renaud Le Gac, Marseille 2. Extract some concepts 1 st March 2012 TELL 40 firmware kick-off 1 /15 7 cyril. drancourt@lapp. in 2 p 3. fr

Hight Level Processing COMMON Event building and processing MEP building DDR 3 Tests PCI-express Ck + throttle x-FPGA GBT Low Level Interface USER 10 Gb. E DCB (1) from Jean-Pierre, 13 oct 2011 Renaud, 23 janv 2012 TELL 40 firmware kick-off 2 /15 7 cyril. drancourt@lapp. in 2 p 3. fr

from Guido, 13 oct 2011 TELL 40 firmware kick-off 3 /15 7 cyril. drancourt@lapp. in 2 p 3. fr

from Xavier, 10 fev 2011 TELL 40 firmware kick-off 4 /15 7 cyril. drancourt@lapp. in 2 p 3. fr

SUMMARY TELL 40 firmware kick-off 5 /15 7 cyril. drancourt@lapp. in 2 p 3. fr

MEP Format • It is not clear to me that MEP builder is a common firmware module. • Is it necessary to create a new format for 40 MHz flow or can we keep the current format? • I think we need a specific meeting with Online team and TELL 40 users about MEP format. TELL 40 firmware kick-off 6 /15 7 cyril. drancourt@lapp. in 2 p 3. fr

from Renaud, 23 janv 2012 ? We don’t know yet if we’ll have necessary ressources at LAPP 1 st March 2012 TELL 40 firmware kick-off 7 /15 7 cyril. drancourt@lapp. in 2 p 3. fr