Finite State Machines in Verilog CS 153 Spring

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Finite State Machines in Verilog CS 153, Spring 2007 Ian G. Harris Department of

Finite State Machines in Verilog CS 153, Spring 2007 Ian G. Harris Department of Computer Science University of California Irvine

FSM Implementations • FSM could be implemented structurally, but behavioral is better 11 Detector

FSM Implementations • FSM could be implemented structurally, but behavioral is better 11 Detector - Detects a 11 sequence on input w reset w=1 w=0 A/z=0 B/z=0 w=1 w=0 C/z=1 w=1 • Moore machine - Output depends on state, not inputs • Output is z, inputs are w and reset • Z set to 1 when 11 occurs on input w

Moore Machine Structure inputs Next state logic Output logic State Elements Current state •

Moore Machine Structure inputs Next state logic Output logic State Elements Current state • Verilog code will have this structure as well outputs

FSM Verilog, Next State Logic module one_det (Clock, Resetn, w, z) input Clock, Resetn,

FSM Verilog, Next State Logic module one_det (Clock, Resetn, w, z) input Clock, Resetn, w; output z; reg [2: 1] y, Y; parameter [2: 1] A=2’b 00, B=2’b 01, c=2’b 10; always @(w or y) case (y) A: if (w) Y=B; else Y=A; B: if (w) Y=C; else Y=A; C: if (w) Y=C; else Y=A; default: Y=2’bxx; endcase • Each state is a branch of the case • Each transition is a branch of an if

Alternative Next State Logic always @(w or y) if (!w) Y = A; else

Alternative Next State Logic always @(w or y) if (!w) Y = A; else case (y) A: Y=B B: Y=C; C: Y=C; default: Y=2’bxx; endcase • Why is this different from the original definition?

FSM Verilog, State Elements and Output Logic always @(negedge Resetn or posedge Clock) if

FSM Verilog, State Elements and Output Logic always @(negedge Resetn or posedge Clock) if (Resetn == 0) y<=A; else y<=Y; assign z = (y==C); Alternative for Output Logic always @(y) if (y == C) z = 1; else z = 0;