Figure 5 2 Halfadder Figure 5 4 Fulladder

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Figure 5. 2. Half-adder.

Figure 5. 2. Half-adder.

Figure 5. 4. Full-adder.

Figure 5. 4. Full-adder.

x 7 c 7 x 0 A : a 7 a 0 y 7

x 7 c 7 x 0 A : a 7 a 0 y 7 y 0 s 7 s 0 0 x 8 x 7 c 8 P = 3 A : P 9 x 0 y 8 y 7 y 0 s 8 s 0 P 8 P 0 (a) Naive approach A : a 7 0 x 8 c 8 P = 3 A : P 9 x 1 x 0 a 0 0 y 8 y 7 y 0 s 8 s 0 P 8 P 0 (b) Efficient design Figure 5. 7. Circuit that multiplies an 8 -bit unsigned number by 3.

Multiplicand M Multiplier Q (14) (11) 1110 ´ 1011 1110 0000 1110 Product P

Multiplicand M Multiplier Q (14) (11) 1110 ´ 1011 1110 0000 1110 Product P (154) 10011010 (a) Multiplication by hand Multiplicand M Multiplier Q (11) (14) Partial product 0 Partial product 1 Partial product 2 Product P (154) 1110 ´ 1011 1110 + 1110 10101 + 0000 01010 + 1110 10011010 (b) Multiplication for implementation in hardware Figure 5. 35. Multiplication of unsigned number.

Figure 5. 36. A 4 x 4 multiplier circuit.

Figure 5. 36. A 4 x 4 multiplier circuit.

Multiplicand M Multiplier Q (+14) (+11) Partial product 0 0 00 1 1 1

Multiplicand M Multiplier Q (+14) (+11) Partial product 0 0 00 1 1 1 0 + 001110 Partial product 1 0010101 + 000000 Partial product 2 00 0 1 0 + 00 1 1 1 0 Partial product 3 Product P 01110 x 01011 00 1 0 0 1 1 + 000000 (+154) 0010011010 (a) Positive multiplicand M Multiplier Q (– 14) (+11) Partial product 0 1 11 0 0 1 0 + 11 0 0 1 0 Partial product 1 11 0 1 1 + 00 0 0 Partial product 2 11 1 0 1 + 11 0 0 1 0 Partial product 3 Product P 10010 ´ 01011 11 0 1 1 0 0 + 000000 (– 154) 110110 (b) Negative multiplicand Figure 5. 37. Multiplication of signed numbers.

Table 5. 4. The seven-bit ASCII code.

Table 5. 4. The seven-bit ASCII code.