FIFO introduction The function of the FIFO Data

FIFO introduction

The function of the FIFO • Data width converter – IP may use different data width. Data width converter can be integrate into FIFO easily without performance lost. • Synchronize different data rate IP – IP may have different data rate. Without FIFO it is impossible to connect them together. • Input and output FSM – IP may have it’s own input and output behavior. We can integrate the FSM into the FIFO.

The primitive signals - FIFO 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. CLK RESETN DATAIN DATAOUT READ or IP_LOAD WRITE EMPTY FULL FIFO_STOP FIFO_RM_FULL FIFO_WM_FULL

The primitive signals - GLOBAL 1. PIN_VCC 2. PIN_GND 3. ENABLE

FIFO signal introduction - READ or IP_LOAD • READ or IP_LOAD – READ signal means that the IP is active. The IP will tell the FIFO when to send the new data. – IP_LOAD signal means that the IP is passive. The IP execute on fixed cycles. The FIFO will send the IP_LOAD signal to tell the IP new data is ready.

FIFO signal introduction - FIFO_STOP • FIFO_STOP – FIFO_STOP signal in the IP is used to indicate that when the IP should send the FIFO_RM_FULL signals. The FIFO_STOP value must be at least the pipeline depth of the previous IP. Otherwise, there will be buffer-overflow.

FIFO signal introduction - FIFO_RM_FULL , FIFO_WM_FULL • FIFO_RM_FULL – FIFO_RM_FULL signal is used to inform previous FIFO that this FIFO can’t send output data in time. So the previous FIFO should stop feed data into this IP. • FIFO_WM_FULL – FIFO_WM_FULL signal is used to inform this FIFO that next FIFO can’t send output data in time. So this FIFO should stop feed data into this IP. The FIFO_WM_FULL and FIFO_RM_FULL become a chain.

IP description

The IP description - required data • IP port declaration • IP port mapping • IP input and output behavior – This is the most difficult part • INTERFACE PARAMETER – FIFO data width

Example 1 AES - Port declaration • We use Verilog type declaration • input clk; input rst; input ld; input [127: 0] key; input [127: 0] text_in; output done; output [127: 0] text_out;

Example 1 AES - Port mapping • We use Verilog type mapping • aes_cipher_top(. clk(CLK), . rst(RESETN), . ld(IP_LOAD), . key(AES_KEY), . text_in(DATAOUT), . done(WRITE), . text_out(DATAIN));

Example 1 AES - input behavior S 1 : S 2 : S 3 : S 4 : S 5 : S 6 : S 7 : S 8 : S 9 : IP_LOAD <= 1’b 1; IP_LOAD <= 1’b 0; IP_LOAD <= 1’b 0; S 10 : IP_LOAD <= 1’b 0; S 11 : IP_LOAD <= 1’b 0; S 12 : IP_LOAD <= 1’b 0;

Example 1 AES - output behavior • The AES use done signal to indicate that the output data is valid. It didn’t have special output behavior. So leave it blank.

Example 1 AES - Interface parameter • FIFO data width – This is an important parameter. The data width converter will be automatic generated according to this parameter. – The AES use 128 -bits data width. – FIFO_DATA_WIDTH_IN = 128; – FIFO_DATA_WIDTH_OUT = 128;

Example 2 RS-DECODER - Port declaration input CLK; input RESET; input DATA_VALID_IN; Input E_D; input [7: 0] DATA_IN; output DATA_VALID_OUT; output [7: 0] DATA_OUT;

Example 2 RS - DECODER - Port mapping RS_5_3_GF 256 rs_decoder(. CLK(CLK), . RESET(RESETN), . DATA_VALID_IN(IP_LOAD), . DATA_IN(DATAOUT), . E_D(PIN_GND), . DATA_VALID_OUT(WRITE), . DATA_OUT(DATAIN));

Example 2 RS-DECODER - input behavior S 1 : IP_LOAD <= 1’b 1; DATAOUT <= FIFO_DATA[7: 0]; S 2 : IP_LOAD <= 1’b 1; DATAOUT <= FIFO_DATA[15: 8]; S 3 : IP_LOAD <= 1’b 1; DATAOUT <= FIFO_DATA[23: 16]; S 4 : IP_LOAD <= 1’b 1; DATAOUT <= FIFO_DATA[31: 24]; S 5 : IP_LOAD <= 1’b 1; DATAOUT <= FIFO_DATA[39: 32];

Example 2 RS-DECODER - output behavior S 1 : IF(WRITE == 1’b 1) FIFO_DATA <= DATAIN; S 2 : IF(WRITE == 1’b 1) FIFO_DATA <= DATAIN; S 3 : IF(WRITE == 1’b 1) FIFO_DATA <= DATAIN; S 4 : IF(WRITE == 1’b 1) FIFO_DATA <= FIFO_DATA; S 5 : IF(WRITE == 1’b 1) FIFO_DATA <= FIFO_DATA;

Example 2 RS-DECODER - interface parameter • FIFO_DATA_WIDTH_IN = 40; • FIFO_DATA_WIDTH_OUT = 8;

Example 3 ACCUMULATOR - Port declaration input clk; input nreset; input enable; input fifo_empty; input [31: 0] din; input [4: 0]latency; output [31: 0] dout; output done; output ack;

Example 3 ACCUMULATOR - Port declaration ip_accumulator(. clk(CLK), . nreset(RESETN), . enable(ENABLE), . fifo_empty(FIFO_EMPTY), . latency(LATENCY), . din(DATAOUT), . dout(DATAIN), . done(WRITE), . ack(READ));

Example 3 ACCUMULATOR - input behavior • Since accumulator use read signal, it didn’t have special input behavior.

Example 3 ACCUMULATOR - output behavior • The accumulator didn’t have special output behavior.

Example 3 ACCUMULATOR - interface parameter • FIFO_DATA_WIDTH_IN = 32; • FIFO_DATA_WIDTH_OUT = 32;

IP connection description

Components • BUS COMPONENT – am_readmaster_pipeline – am_readmaster – am_writemaster • IP – – – ip_accumulator rs_decoder rs_encoder aes_cipher_top aes_invcipher_top

Connection rule • S -> – Element • Element -> – Element , (componentx) – (componentx) • Componentx -> – Componentx, componentx – Component

Example • • • S Element , (componentx) , (componentx) Element , (componentx) • (componentx) , (componentx) • (am_readmaster_pipeline), (aes_cipher_top), (rs_encoder, rs_encoder), (am_writemaster)