FIFO design and FIFO lab Jizhe Zhang Overview
FIFO design and FIFO lab Jizhe Zhang
Overview • A brief review (or introduction? ) of FIFO design • n bit pointers vs n+1 bit pointers • FIFO lab introduction • You need to use the FIFO to implement a given objective
FIFO review • We are discussing about synchronous FIFO. • Interface between the producer and the consumer. • The consumer should receive the data in the same order as the producer is sending the data Does it work? Works, but inefficient
Write pointer and read pointer • WP: The next location to be deposited (currently points to an unoccupied location if the FIFO is not full) • Incremented after the producer deposits the data • RP: The next location to be consumed (currently points to a occupied location if the FIFO is not empty) • Incremented after the consumer reads the data • WEN and REN signals (illustrated by waveforms)
n bits vs n+1 bits pointers •
(n+1)-bit pointers • Take n=2 for example • 4 locations in the FIFO • WP-RP=000: empty • WP-RP=100: full • What’s the range of WP-RP? • Is it possible that WP-RP=100… 01?
n-bit pointers with almost_full and almost_empty flags • The basic idea (take n=3 (8 -loc FIFO) for example) • For n-bit pointers, the only problem is when WP -RP=000. • Before WP-RP=000, does it hit WP-RP=10 x first, or WP-RP=01 x first? Almost full • 10 x first: WP-RP is 111 ->000. Full. • 01 x first: WP-RP is 001 ->000. Empty. Almost empty
Implementation of n-bit pointers with flags • When WP-RP starts with 01, it’s almost empty. • If WP-RP=000 under this state, then the FIFO is empty. • When WP-RP starts with 10, it’s almost full. • If WP-RP=000 under this state, then the FIFO is full. • We use flip-flops to store the state. • The state is not changed when WP-RP starts with 00 or 11.
2 -clock FIFO • The producer and the customer are not using the same clock signal. • The FIFO is crossing two clock domains. • Please watch Prof. Puvvada’s video.
FIFO lab • First part: finish the n-bit FIFO design. • Second part:
M 28 52 11 63 66 A 8 97 35 FIFO N
Extreme case M 28 12 14 16 17 A 9 21 19 FIFO N
State machine of the design • M and N have each only one port • At most one reading / writing at each clock. • At each clock we follow the logic below (this helps you to complete the Interleave state • If we are looking for an even number to go into N, then we see if senior even numbers are waiting in the FIFO. If so we need to transfer the senior-most even number from the FIFO to N. At that time, if the current M[I] is an even number, then that number is drawn and added to the FIFO at the end of the queue (as the juniormost even number). Please note that these two transfers happen at the same time. • Actually if there are senior even numbers in the FIFO, if the current M[I] is an even number, it has to go the end of the queue in the FIFO irrespective of what N is looking for. • If we are looking for an even number to go into N, and if the FIFO does not have even numbers in it (may be because it has odd numbers or may be because it is empty), then we see if the current M[I] is an even number. If it is, we transfer it to N[J]. If M[I] is an odd number, it is added to the FIFO.
M 29 51 12 65 67 A 8 98 34 FIFO N
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