FEC Linear Block Coding Matthew Pregara Zachary Saigh

FEC Linear Block Coding Matthew Pregara & Zachary Saigh Advisors: Dr. In Soo Ahn & Dr. Yufeng Lu Dept. of Electrical and Computer Eng.

2 Table of Contents Motivation Introduction Hamming Code Example Tanner Graph/Hard Decision Decoding Simulink Simulation on Hamming Code VHDL Simulation Results Low Density Parity Check Code Timeline and Division of Labor Conclusion

3 Motivation FEC: Forward Error Correction Adds redundancy to message. Detects AND Corrects Errors. ARQ: Automatic Repeat Request Detects errors and requests retransmission.

4 Motivation (taken from [1])

5 Redundancy Add extra bits (Parity Bits) to message. Increases number of bits sent, requiring larger transmission bandwidth. Decreases number of errors in message. Parity bits Information from multiple message bits

6 Linear Block Coding Block Codes are denoted by (n, k). k = message bits (message word) n = message bits + parity bits (codeword) # of parity bits: m = n - k Code Rate R = k/n Example: (7, 4) code 4 message bits +3 parity bits = 7 codeword bits Code rate R = 4/7

7 Block Coding Diagram

8 Linear Block Coding cont.

Error Detection

10 Hamming Code G matrix is derived from a primitive polynomial, a factor of xn +1. Systematic G matrix is obtained from G matrix. H matrix is determined from systematic G matrix. G = [Ik | P], where P = parity matrix H = [PT | In-k]; HT =

11 Encoding Message m, made of k bits, is post-multiplied by the G matrix using Modulo-2 arithmetic.

12 Constructing G Starts with xn+1, Factorize x 7+1 n = 7. = (x+1)(x 3+x 2+1)(x 3+x+1). Find solution for one of the terms. (x 3+x 2+1) => [1 1 0 1]

13 Fill matrix with solution (shifting 1 entry in each row) Find RREF Fill empty entries with 0’s Result is the systematic G matrix I 4 P

14 Encoding

15 Encoding Example

16 Decoding Received codeword of n bits is post-multiplied by HT to obtain the syndrome.

17 Decoding Recall: G = [Ik | P]; P = parity matrix H = [PT | In-k ] S = syndrome

18 Syndrome Table

19 Example continued

20 Correcting Errors In this case the 2 nd bit is corrupted Invert the corrupted bit according to the location found by the syndrome table

21 Tanner Graph and Hard Decision Decoding (8, 4) Example (2458) (1236) (3678) (1457)

22 Hard Decision Decoding Check Nodes C 1 C 2 C 3 C 4 Activities Receive V 2→ 1 V 4→ 1 V 5→ 0 V 8→ 1 Send 0 → V 2 0 → V 4 1 → V 5 0 → V 8 Receive V 1→ 1 V 2→ 1 V 3→ 0 V 6→ 1 Send 0 → V 1 0 → V 2 1 → V 3 0 → V 6 Receive V 3→ 0 V 6→ 1 V 7→ 0 V 8→ 1 Send 0 → V 3 1 → V 6 0 → V 7 1 → V 8 Receive V 1→ 1 V 4→ 1 V 5→ 0 V 7→ 0 Send 1 → V 1 1 → V 4 0 → V 5 0 → V 7

23 Variable Node Decisions Variable Nodes yi Messages from Check Nodes Decision V 1 1 C 2 → 0 C 4 → 1 1 V 2 1 C 1 → 0 C 2 → 0 0 V 3 0 C 2 → 1 C 3 → 0 0 V 4 1 C 1 → 0 C 4 → 1 1 V 5 0 C 1 → 1 C 4 → 0 0 V 6 1 C 2 → 0 C 3 → 1 1 V 7 0 C 3 → 0 C 4 → 0 0 V 8 1 C 1 → 0 C 3 → 1 1

24 Simulink Model of (7, 4) Hamming Code

26 Simulation Results Field Programmable Gate Array(FPGA)

27 Encoding Decoding

28 Simulation Results Hardware Description Language

29 Low Density Parity Check Code Offers performance close to Shannon’s channel capacity limit. Can correct multiple bit errors. Low decoder complexity.

(taken from [1]

31 LDPC Code Start with H matrix first The entries of 1 in H are sparsely populated From the H matrix, find the systematic G matrix The entries of 1 in G are not sparsely populated, causing encoder complexity.

32 LDPC Code Decoding is done iteratively. To operate close to Shannon limit under very low SNR, the dimensions of H matrix are very large. For real-time operations, the dimensions of H matrix are constrained by hardware , and decoding time allowed, and others.

Division of Labor Zack MATLAB Encoder Simulink design of encoder/channel Implementation of VHDL on FPGA Performance analysis of FPGA implementaiton Matt MATLAB Decoder Simulink design of Decoder Implementation of Xilinx system generator Performance analysis of MATLAB/Simulink implementation

Timeline

35 Conclusion LDPC coding is to be implemented. Preliminary investigations are performed. Examined Hamming coder/decoder under Matlab and Simulink environment. Tanner graph representation of LDPC examples researched. Plans to choose an LDPC coding scheme and to implement it using FPGA.

36 References [1] Valenti, Matthew. Iterative Solutions Coded Modulation Library Theory of Operation. West Virginia University, 03 Oct. 2005. Web. 23 Oct. 2012. <www. wvu. edu>. [2] B. Sklar, Digital Communications, second edition: Fundamentals and Applications, Prentice-Hall, 2000. [3] Xilinx System Generator Manual, Xilinx Inc. , 2011.

37 Q and A’s Thank you for listening. Any questions or suggestions are welcome.