Feb 17 2011 Midterm overview Real life examples

Feb. 17, 2011 • Midterm overview • Real life examples of built chips – Clock Skew • Arithmetic • Data Centers • Power reduction techniques – Dynamic Voltage / Frequency Scaling – Clock Throttling – Power Gating – Others? • Project – 4 b adder with Razor recovery

Go Over Problems • 1 c • 2 a; 2 b • 3 c

Crossbar Design

Mirror Adder Stick Diagram 6

The Mirror Adder • The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carrygeneration circuitry. • When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important. • The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. • The transistors connected to Ci are placed closest to the output. • Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size. 7

Transmission Gate Full Adder 8

Manchester Carry Chain 9

Manchester Carry Chain 10

Carry-Bypass Adder Also called Carry-Skip 11

Carry-Bypass Adder (cont. ) 12

Carry Ripple versus Carry Bypass 13

Carry-Select Adder 14

Carry Select Adder: Critical Path 15

Linear Carry Select 16

Square Root Carry Select 17

Adder Delays - Comparison 18

Look. Ahead - Basic Idea 19

Look-Ahead: Topology Expanding Lookahead equations: All the way: 20

Carry Lookahead Trees Can continue building the tree hierarchically. 21

Power Reduction Techniques • Stop the clock – Dynamic power reduction • Power gating – Reduce the leakage • How fast can you turn something on/off? – Nothing to do sleep • How can you save power while in operation? – Near-threshold design

Power Gating

Kevin Nowka, IBM

Gate Leakage

Digital Parallelization Y[n] = X[n] + X[n-1] Analog Signal Input (5 bits @ 5 GS/s) X[n-1] clk X[n] clk x Or + (8 bits @ 100 MHz) Clk = 5 GHz ANALOG DIGITAL Y[n]

DSP Parallelization Y[n] = X[n] + X[n-1] Y[n-1] = X[n-1] + X[n-2] Input (5 bits @ 5 GS/s) clk X[n] clk + x + clk X[n-1] clkb x clk CLK = 5 GHz CLK = 2. 5 GHz Y[n] Y[n-1]

DSP Parallelization • Clock speed reduced by ½ – Can parallelize further – Increase number of MACs(multiply/accumulates) by 2 • Intuition? – Area goes up by 2 – Power decreases (clock rate down by 2, computations up by 2, but easier timing constraints) – What about clock power? • Save a little power, but double the area?

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation • http: //www. eecs. umich. edu/~taustin/papers/ MICRO 36 -Razor. pdf

Project Description • Minimal: 4 b Adder, Implemented with Razor – Simulations into near-threshold domain • Grad. Student: requires more advanced design – Analog: Opamps built using inverters – Digital: Adiabatic Near-Threshold – Power Gating: add power gating to your design • Undergrad: extra credit if do any of the above

Problem 1: On-Chip Wires Consume Energy • On-chip wire power does not scale – Dominated by interconnect capacitance (CVDD 2) ON-CHIP (Status Quo): 100 - 300 f. J/bit/mm OUR GOAL: < 5 f. J/bit/mm NOTE: Sub/Near-Threshold doesn’t help this problem! [DOE, Exascale Workshop]

Data Center Design • http: //www. spectrum. ieee. org/feb 09/7327