Fast Waveform Digitizing in Radiation Detection using Switched

Fast Waveform Digitizing in Radiation Detection using Switched Capacitor Arrays Stefan Ritt Paul Scherrer Institute, Switzerland

Question ? 4 channels 5 GSPS 1 GHz BW 8 bit (6 -7) 15 k$ Sept 25 th, 2009 4 channels 5 GSPS 1 GHz BW 11. 5 bits 1 k$ USB Power CMOS ET Vancouver 2

The need for speed Q-ADC • Traditional technique Det chan • Gated charge ADCs • Constant Fraction Disc. • Time-to-Digital Conv. TDC Disc. • High rate applications Det chan FADC Needed: >3 GSPS 12 bit hits • Pile-up becomes an issue Waveform digitizing • Issues: Limited speed and resolution Trigger • High channel counts • Power consumption • FADC Costs Moving average baseline Sept 25 th, 2009 CMOS ET Vancouver 3

Switched Capacitor Array 0. 2 -2 ns Inverter “Domino” ring chain IN Waveform stored Clock Shift Register Out FADC 33 MHz “Time stretcher” GHz MHz Sept 25 th, 2009 CMOS ET Vancouver 4

DRS 4 • Designed for the MEG experiment at PSI, Switzerland • UMC 0. 25 mm 1 P 5 M MMC process (UMC), 5 x 5 mm 2, radiation hard • 8+1 ch. each 1024 cells • Differential inputs, differential outputs • Sampling speed 700 MHz … 5 GHz, PLL stabilized • Readout speed 30 MHz, multiplexed or in parallel Sept 25 th, 2009 CMOS ET Vancouver 5

Comparison with other chips MATACQ D. Breton LABRADOR G. Varner DRS 4 this talk Bandwidth (-3 db) 300 MHz > 1000 MHz 950 MHz Sampling frequency 50 MHz… 2 GHz 10 MHz … 3. 5 GHz 700 MHz … 6 GHz Full scale range ± 0. 5 V +0. 4 … 2. 1 V ± 0. 5 V Effective #bits 12 bit 10 bit 11. 5 bit Sample points 1 x 2520 9 x 256 9 x 1024 Frequency PLL YES NO YES Digitization 5 MHz N/A 30 MHz Readout dead time 650 ms 150 ms 3 ms – 370 ms Integral nonlinearity ± 0. 1 % ± 0. 05% Radiation hard No No Yes (chip) Board V 1729 (CAEN) - V 17 xx (CAEN) Sept 25 th, 2009 CMOS ET Vancouver 6

Switched Capacitor Array • Pros (DRS 4 chip) • High speed (5 GHz) high resolution (11. 5 bit resol. ) • High channel density (9 channels on 5 x 5 mm 2) • Low power (10 -40 m. W / channel) • Low cost (~ 10$ / channel) • Cons s n o i • No continuous acquisition at t i im L e z i • Limited nsampling depth m i i M : al o • Nonlinear timing G Sept 25 th, 2009 CMOS ET Vancouver Dt Dt Dt 7

How to minimize dead time ? • Fast analog readout: 30 ns / sample • Parallel readout • Region-of-interest readout • Simultaneous write / read AD 9222 12 bit 8 channels Sept 25 th, 2009 CMOS ET Vancouver 8

ROI readout mode delayed trigger normal stop trigger stop after latency Trigger Delay stop 33 MHz e. g. 100 samples @ 33 MHz 3 us dead time 300, 000 events / sec. Sept 25 th, 2009 readout shift register Patent pending! CMOS ET Vancouver 9

Daisy-chaining of channels Domino Wave clock 1 enable input Channel 0 0 enable input Channel 1 1 Channel 2 0 Channel 3 1 Channel 4 0 Channel 5 1 Channel 6 0 Channel 7 1 Channel 7 DRS 4 can be partitioned in: 8 x 1024, 4 x 2048, 2 x 4096, 1 x 8192 cells Chip daisy-chaining possible to reach virtually unlimited sampling depth Sept 25 th, 2009 CMOS ET Vancouver 10

Simultaneous Write/Read FPGA 0 1 Channel 0 0 1 Channel 1 1 0 Channel 2 0 Channel 3 0 Channel 4 0 Channel 5 0 Channel 6 0 Channel 7 readout 8 -fold analog multi-event buffer Expected crosstalk ~few m. V Sept 25 th, 2009 CMOS ET Vancouver 11

Interleaved sampling delays (167 ps/8 = 21 ps) 6 GSPS * 8 = 48 GSPS G. Varner et al. , Nucl. Instrum. Meth. A 583, 447 (2007) Possible with DRS 4 if delay is implemented on PCB Sept 25 th, 2009 CMOS ET Vancouver 12

Trigger and DAQ on same board DRS 4 trigger DRS MUX • DRS readout (5 GHz samples) though same 8 -channel FADCs analog front end • FPGA can make local trigger (or global one) and stop DRS upon a trigger FADC 12 bit 65 MHz FPGA global trigger bus • Using a multiplexer in DRS 4, input signals can simultaneously digitized at 65 MHz and sampled in the DRS LVDS SRAM “Free” local trigger capability without additional hardware Sept 25 th, 2009 CMOS ET Vancouver 13

Performance of SCA Chips Test Results

Bandwidth • Passive Input: Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ? ? ? (flip-chip) • Active Inputs: ~300 MHz with current CMOS technology (MATACQ) QFP package • Near future: 130 nm technology might improve this slightly 850 MHz (-3 d. B) Measurement Sept 25 th, 2009 CMOS ET Vancouver 15

Timing jitter • Inverter chain has transistor variations Dti between samples differ “Fixed pattern aperture jitter” • “Differential temporal nonlinearity” TDi= Dti – Dtnominal • “Integral temporal nonlinearity” TIi = SDti – i Dtnominal • “Random aperture jitter” = variation of Dti between measurements Dt 1 Dt 2 Dt 3 Dt 4 Dt 5 TD 1 Sept 25 th, 2009 TI 5 CMOS ET Vancouver 16

Fixed jitter calibration • Fixed jitter is constant over time, can be measured and corrected for • Several methods are commonly used • Most use sine wave with random phase and correct for TDi on a statistical basis Sept 25 th, 2009 CMOS ET Vancouver 17

Fixed Pattern Jitter Results • TDi typically ~50 ps RMS @ 5 GHz • TIi goes up to ~600 ps • Jitter is mostly constant over time, measured and corrected • Residual random jitter (RMS) • 25 ps MATACQ • 10 ps Labrador • 3 -4 ps DRS 4 SCA technology can replace high resolution TDCs Sept 25 th, 2009 CMOS ET Vancouver 18

Applications of SCA Chips What can we do with this technology?

On-line waveform display S 848 PMTs “virtual oscilloscope” template fit click pedestal histo Sept 25 th, 2009 CMOS ET Vancouver 20

Pulse shape discrimination Example: a/g source in liquid xenon detector (or: g/p in air shower) a g Leading edge Sept 25 th, 2009 Decay time AC-coupling CMOS ET Vancouver Reflections 21

t-distribution ta = 21 ns tg = 34 ns a Waveforms can be clearly distinguished g Sept 25 th, 2009 CMOS ET Vancouver 22

Template Fit • Determine “standard” PMT pulse by averaging over many events “Template” pb Experiment 500 MHz sampling • Find hit in waveform • Shift (“TDC”) and scale (“ADC”) template to hit • Minimize c 2 • Compare fit with waveform • Repeat if above threshold • Store ADC & TDC values Pile-up can be detected if two hits are separated in time by ~rise time of signal Sept 25 th, 2009 CMOS ET Vancouver 23

Experiments using DRS chip MEG 3000 channels DRS 4 MAGIC-II 400 channels DRS 2 BPM for XFEL@PSI 1000 channels DRS 4 (planned) MACE (India) 400 channels DRS 4 (planned) Sept 25 th, 2009 CMOS ET Vancouver PET 24

Datasheet http: //drs. web. psi. ch/datasheets Sept 25 th, 2009 CMOS ET Vancouver 25

Evaluation Board • DRS 4 can be obtained from PSI on a “non-profit” basis • Delivery “as-is” • Costs ~ 15 -20 CAN$/chn • USB Evaluation board as reference design • Anybody wants to build a pocket scope? Sept 25 th, 2009 CMOS ET Vancouver 26

Conclusions • This is Exciting Stuff! • DRS 4 has 6 GHz, 1024 sampling cells per channel, 9 channels per chip, 11. 5 bit vertical resolution, 4 ps timing accuracy, other chips similar • More development in the pipeline • Fast waveform digitizing with SCA chips will have a big impact on particle detection in the next future • Other fields should benefit from this development LABRADOR: http: //www. phys. hawaii. edu/~idlab/ MATACQ: http: //matacq. free. fr/ DRS 4: http: //drs. web. psi. ch Sept 25 th, 2009 CMOS ET Vancouver 27