Fast MinRegister Retiming Through Binary MaxFlow Aaron Hurst

Fast Min-Register Retiming Through Binary Max-Flow Aaron Hurst Alan Mishchenko Robert Brayton FMCAD 2007

Retiming l Retiming is the structural relocation of registers such that output functionality is preserved l Registers can be relocated to one of several ends l l l Minimizing worst-case delay Minimizing number of registers Either of the above under constraints Optimally or heuristically Other… ? In this work, we look at optimal register minimization without delay constraints: “Min-register”

Why Min-Register? Register count is critical in sequential verification l “Make or break” effect State representation: linear decrease Total state space: exponential decrease Reachable state space: potential decrease l Low investment l Evidence of net utility l l Academic investigation: Cabodi, Quer, Somenzi DAC ‘ 01 Commercial sequential verification tools!

Orientation l Consider one combinational frame of the circuit l A single directed acyclic graph of combinational logic l l Nodes: Edges: Inputs: Outputs: logic gates pair-wise net connections register outputs, primary inputs registers inputs, primary outputs primary inputs register outputs

Cuts in a Frame l Momentarily ignore all primary IOs and their transitive fan-in/out l l Retiming = a complete cut of the DAG Number of registers = l Problem consists of finding minimum cut

Max-Flow Formulation l Min-cut/Max-flow Duality l l 1. 2. Edges in graph are assigned a capacity Min-cut width = Max-flow through graph sink Compute flow Partition graph into {S, R}, S R = l l l S = an augmenting path exists from source to s R = no augmenting path exists from source to r Reachable versus unreachable residual graph source

Closest Min-Cut l Insert registers between a node and any fanout that lies in the other partition l sink Fast: remove old registers; insert new ones l Min-cut is not unique l Minimum movement of registers source

Unconstrained Flow l Width of minimum cut = capacity of crossing edges 1 1 1 l Effect of unconstrained edges? Restrict location of finite cut l A useful tool… l ? =2

Reverse Edges l l Min-cut guarantees every path will be cut at least once Retiming requires that every path is cut exactly once R 2’ R 1 R 2 R 3’ R 3 l A cut must be crossed by a reverse edge to have a path with more than one crossing l Solution: Use unconstrained flow to prevent reverse edges

Fanout Sharing l Flow graph is composed of arcs 1 1 l False model of register count l l l 1 One register per hyperedge “Fanout sharing” Introduce a structure to simulate fanout-sharing 1 1 1 1 1 1

Single Iteration l n What does the final flow graph look like? Reverse Edges 1 1 1 n Fanout-sharing n l One constraint per node output (not edge) l Binary marking scheme Flow computed on original graph 1 1 1 Unitary Flow Simplification l 1 1 1

Primary Inputs/Outputs l Synchronization with environment is flexible l Registers can be absorbed from / donated to environment… or not l Constrain growth of additional initialization logic sink l PI “Switching off” desynchronization: exclude TFO of primary I/Os Forward retiming past this node Increases latency through PI by 1 PO Logic PI source

Multiple Frames l Thus far, we have only considered retiming within one combinational frame l l l At most one register is moved across a node Global min-cut may stretch across multiple combinational frames l May require moving multiple registers across a node Solution: Repeat over single frame l Logic Terminate when no further change Logic

Forward and Backward l Backward retiming must also be considered l l l Solution for sequential core has already been found Considers retiming in fan-out cone of inputs Backward retiming is identical, with roles of PIs, POs, sources, and sinks reversed Logic

Overall Algorithm Start Forward retiming Backward retiming Block Fan-out Cone of PIs? Block Fan-in Cone of POs? Compute Max-Flow Implement Min-Cut Yes Improv. ? No Yes Implement Min-Cut Improv. ? No l Forward retiming is preferred b/c of initial state computation Done

Asymptotic Analysis l Minimum-register retiming can also be solved using other methods l Original formulation: LP l The Competition: Min-cost flow using cost scaling [Goldberg 97] l Our Algorithm: Single iteration limited by maximum flow Or, using unitary flow simplification… l Total number of iterations is bounded by |R|

Scalability l Each iteration is strictly better than the previous l Runtime can be bounded any intermediate result accepted l l Register Savings per Iteration At the low, low cost of suboptimality The “real” improvement over previous techniques

Experimental Results l Applied to Open. Cores designs l Reduction in number of registers l l l Cost in delay l l Average = -11% Maximum = -62. 5% Average = +25. 8% Runtime is 5 x faster than minimum-cost formulation l <0. 01 s for 70% of benchmarks

Conclusions l Max-flow approach to minimizing register count l Optimal solution with minimum register movement l Handles different models of environment synchronization l Faster than existing methods l l l Algorithmically and practically easier network problem Allows simplification via binary marking Scalable