Fabrication Technology1 n MOS Fabrication CMOS Fabrication pwell

Fabrication Technology(1) • n. MOS Fabrication • CMOS Fabrication – p-well process – n-well process – twin-tub process

Fabrication Technology(2) • All the devices on the wafer are made at the same time • After the circuitry has been placed on the chip – the chip is overglassed (with a passivation layer) to protect it – only those areas which connect to the outside world will be left uncovered (the pads) • The wafer finally passes to a test station – test probes send test signal patterns to the chip and monitor the output of the chip • The yield of a process is the percentage of die which pass this testing • The wafer is then scribed and separated up into the individual chips. These are then packaged

Fabrication Technology(3)

Fabrication Technology(4) Photolithography process

Fabrication Technology(5) Resists • negative: areas to be preserved are hardened after exposure to light • positive: areas to be preserved are not exposed to light Exposure UV light used to sensitize the resist using a mask. Develop Resist areas that are exposed (positive) or not exposed (negative) are removed with an acid and water wash. resist protected area resist exposed area

Fabrication Technology(6) Etch Areas that are exposed and not protected by the resist are etched with an acid and water wash. What is left are, depending on the layer being worked on, are patterns that expose underlying layers.

Cmos Inverter Fabrication

Layout of an Inverter Back is metallized to provide a good ground connection

Step 1: Make the N-Well Top view Mask 1 Cross-sectional view

Step 2: Deposit Field Oxide

Step 3: Open Field with Active Mask 2

Step 4: Deposit Gate Oxide The thickness and the quality of the gate oxide are two of the most critical fabrication parameters, since they strongly affect the operational characteristics of the MOS transistor, as well as its long-term reliability.