Fabrication of MOSFETs Introduction and Fabrication Procedure Amit

Fabrication of MOSFETs Introduction and Fabrication Procedure Amit Degada Asst. Professor amitdegada@gmail. com

Introduction • Integrated circuits: many transistors on one chip. • Very Large Scale Integration (VLSI): millions of logic gates + many Mbits of memroy • Complementary Metal Oxide Semiconductor – Fast, cheap, low power transistors • Today: How to build your own simple CMOS chip – CMOS transistors – Building logic gates from transistors – Transistor layout • Rest of the course: How to build a good CMOS chip

A Brief History • 1958: First integrated circuit – Built by Jack Kilby at Texas Instruments with 2 transistors • 2003 – Intel Pentium 4 mprocessor (55 million transistors) – 512 Mbit DRAM (> 0. 5 billion transistors) • 53% compound annual growth rate over 45 years – No other technology has grown so fast so long • Driven by miniaturization of transistors – Smaller is cheaper, faster, lower in power! – Revolutionary effects on society

Annual Sales • 1018 transistors manufactured in 2003 – 100 million for every human on the planet – $100 B business in 2004

Invention of the Transistor • Vacuum tubes ruled in first half of 20 th century Large, expensive, power-hungry, unreliable • 1947: first point contact transistor – John Bardeen and Walter Brattain at Bell Labs

Transistor Types • Bipolar transistors – npn or pnp silicon structure – Small current into very thin base layer controls large currents between emitter and collector – Base currents limit integration density (power dissipation issue) • Metal Oxide Semiconductor Field Effect Transistors – n. MOS and p. MOSFETS – Voltage applied to insulated gate controls current between source and drain – Low power allows very high integration (ideally zero static power)

MOS Integrated Circuits • 1970’s processes usually had only n. MOS transistors – Inexpensive, but consume power while idle Intel 1101 256 -bit SRAM Intel 4004 4 -bit m. Proc • 1980 s-present: CMOS processes for low idle power

Moore’s Law • 1965: Gordon Moore plotted transistor on each chip – Fit straight line on semilog scale – Transistor counts have doubled every 18 months Integration Levels SSI: 10 gates MSI: 1000 gates LSI: 10, 000 gates VLSI: > 10 k gates

Corollaries • Many other factors grow exponentially – Ex: clock frequency, processor performance

Silicon Lattice • Transistors are built on a silicon substrate • Silicon is a Group IV material • Forms crystal lattice with bonds to four neighbors

Dopants • • • Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V (Arsenic): extra electron (n-type) Group III (Boron): missing electron, called hole (p-type)

p-n Junctions • A junction between p-type and n-type semiconductor forms a diode. • Current flows only in one direction

n. MOS Transistor • Four terminals: gate, source, drain, body • Gate – oxide – body stack looks like a capacitor – Gate and body are conductors – Si. O 2 (oxide) is a very good insulator – Called metal – oxide – semiconductor (MOS) capacitor

n. MOS Operation • Body is commonly tied to ground (0 V) • When the gate is at a low voltage: – P-type body is at low voltage – Source-body and drain-body diodes are OFF – No current flows, transistor is OFF

n. MOS Operation Cont. • When the gate is at a high voltage: – Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from source through channel to drain, transistor is ON 0: Introduction Slide 15

p. MOS Transistor • Similar, but doping and voltages reversed – Body tied to high voltage (VDD) – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior

Power Supply Voltage • GND = 0 V • In 1980’s, VDD = 5 V • VDD has decreased in modern processes due to scaling – High VDD would damage modern tiny transistors – Lower VDD saves power (Dynamic power is propotional to C. VDD 2. f. a) • VDD = 3. 3, 2. 5, 1. 8, 1. 5, 1. 2, 1. 0, …

Transistors as Switches • We can view MOS transistors as electrically controlled switches • Voltage at gate controls path from source to drain

CMOS Inverter A 0 1 Y

CMOS Inverter A Y 0 1 0

CMOS Inverter A Y 0 1 1 0

CMOS NAND Gate A B 0 0 0 1 1 Y

CMOS NAND Gate A B Y 0 0 1 1

CMOS NAND Gate A B Y 0 0 1 1 1 0: Introduction Slide 24

CMOS NAND Gate A B Y 0 0 1 1 1

Introduction and Fabrication Procedure

Objective of the Lecture • Design of Logics in CMOS • Why to Study Fabrication? • Flow Diagram. • Fabrication Process Flow: Basic Steps

CMOS NOR Gate A B Y 0 0 1 0 1 0 0 1 1 0

3 -input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high if ANY input is 0

3 -input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high if ANY input is 0

Complementary CMOS • Complementary CMOS logic gates – n. MOS pull-down network – p. MOS pull-up network – a. k. a. static CMOS Pull-up OFF Pull-up ON Pull-down OFF Z (float) 1 Pull-down ON X (crowbar) 0

Series and Parallel • • n. MOS: 1 = ON p. MOS: 0 = ON Series: both must be ON Parallel: either can be ON

Conduction Complement • Complementary CMOS gates always produce 0 or 1 • Ex: NAND gate – Series n. MOS: Y=0 when both inputs are 1 – Thus Y=1 when either input is 0 – Requires parallel p. MOS • Rule of Conduction Complements – Pull-up network is complement of pull-down – Parallel -> series, series -> parallel

Compound Gates • Compound gates can do any inverting function • Ex:

Example: O 3 AI •

Example: O 3 AI

Objective of the Lecture • Design of Logics in CMOS • Why to Study Fabrication? • Flow Diagram. • Fabrication Process Flow: Basic Steps

Why to study Fabrication? • Strong link between Fabrication Process , the circuit design procedure and the performance of resulting chip • The circuit designer must have clear understanding of the roles of various MASKs used in the fabrication procedure and How this MASKs define various feature of the devices on a Chip • To know to create effective design. • To optimize the circuit with respect to various manufacturing parameters.

Well • Requires to build both p. MOS and n. MOS on single wafer. • To accommodate both p. MOS and n. MOS devices, special regions must be created in which the semiconductor type is oppossite of the substrate type. • Also Known as Tubs. • Twin-tubs

Objective of the Lecture • Design of Logics in CMOS • Why to Study Fabrication? • Flow Diagram. • Fabrication Process Flow: Basic Steps

Flow Diagram Create n-Well regions and Channel Stops region Grow Field Oxide and Gate Oxide Deposite and pattern Polysilcon Layer Implant sources, drain regions and substrate contacts Create contact Windows, deposit and pattern metal layer

Objective of the Lecture • Design of Logics in CMOS • Why to Study Fabrication? • Flow Diagram. • Fabrication Process Flow: Basic Steps

Fabrication Procedure Flow: Basic Steps • Masks: Each Processing steps in the fabrication procedure requires to define certain area on the chip. This is known as Masks. • Chips are specified with set of masks • Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) • Feature size f = distance between source and drain – Set by minimum width of polysilicon • Feature size improves 30% every 3 years or so • Normalize for feature size when describing design rules • The ICs are viewed as a set of pattern layers of doped Silicon, Polysilicon, Metal and Insulating Silicon Dioxide. • A layer mut be Patterned before the next layer of material is applied on the chip.

Inverter Cross-section • Typically use p-type substrate for n. MOS transistors • Requires n-well for body of p. MOS transistors

Inverter Cross-section with Well and Substrate taps • • • Typically use p-type substrate for n. MOS transistors Requires n-well for body of p. MOS transistors Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection Use heavily doped well and substrate contacts / taps

Inverter Mask Set • Transistors and wires are defined by masks • Cross-section taken along dashed line

Detailed Mask Views • Six masks – n-well – Polysilicon – n+ diffusion – p+ diffusion – Contact – Metal

Pattern Preparation Chrome Pattern Quartz Substrate Pellicle

Wafer Preparation

Wafer Preparation

Fabrication Steps • Start with blank wafer • Build inverter from the bottom up • First step will be to form the n-well – Cover wafer with protective layer of Si. O 2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off Si. O 2

Oxidation • Grow Si. O 2 on top of Si wafer – 900 – 1200 C with H 2 O or O 2 in oxidation furnace

Photolithography Exposure Processes

Photoresist • Used for lithography. • Lithography is a process used to transfer a pattern to layer on the chip. Similar to Printng Process • Spin on photoresist (about 1 mm thickness) – Photoresist is a light-sensitive organic polymer – Possitive Photoresist: Softens where exposed to light – Negative Photresist: Harden where exposed to light, Not used in practise generally

Lithography • Expose photoresist through n-well mask • Strip off exposed photoresist

Etch Cluster Tool Configuration Wafers Etch Chambers Transfer Chamber Loadlock Gas Inlet RIE Chamber Die-electric Etch Plasma Etch Wafer Transfer Chamber RF Power Exhaust

Etch • Etch oxide with hydrofluoric acid (HF) – Seeps through skin and eats bone; nasty stuff!!! • Only attacks oxide where resist has been exposed

Strip Photoresist • Strip off remaining photoresist – Use mixture of acids called piranah etch • Necessary so resist doesn’t melt in next step

n-well • n-well is formed with diffusion or ion implantation • Diffusion – Place wafer in furnace with arsenic gas – Heat until As atoms diffuse into exposed Si • Ion Implanatation – Blast wafer with beam of As ions – Ions blocked by Si. O 2, only enter exposed Si

Ion Implantation Focus Neutral beam trap and beam gate Beam trap and gate plate Y - axis scanner X - axis scanner Neutral beam and beam path gated Wafer in wafer process chamber

Strip Oxide • Strip off the remaining oxide using HF • Back to bare wafer with n-well • Subsequent steps involve similar series of steps

Polysilicon • Deposit very thin layer of gate oxide – < 20 Å (6 -7 atomic layers) • Chemical Vapor Deposition (CVD) of silicon layer – Place wafer in furnace with Silane gas (Si. H 4) – Forms many small crystals called polysilicon – Heavily doped to be good conductor

Polysilicon Patterning • Use same lithography process to pattern polysilicon

Self-Aligned Process • Use oxide and masking to expose where n+ dopants should be diffused or implanted • N-diffusion forms n. MOS source, drain, and n-well contact

N-diffusion • Pattern oxide and form n+ regions • Self-aligned process where gate blocks diffusion • Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

N-diffusion cont. • Historically dopants were diffused • Usually ion implantation today • But regions are still called diffusion

N-diffusion cont. • Strip off oxide to complete patterning step

P-Diffusion • Similar set of steps form p+ diffusion regions for p. MOS source and drain and substrate contact

Contacts • Now we need to wire together the devices • Cover chip with thick field oxide • Etch oxide where contact cuts are needed

Metalization • Sputter on aluminum over whole wafer • Pattern to remove excess metal, leaving wires

Testing Defective IC Individual integrated circuits are tested to distinguish good die from bad ones.

Die Cut and Assembly Good chips are attached to a lead frame package.

Die Attach and Wire Bonding lead frame gold wire bonding pad connecting pin

Final Test Chips are electrically tested under varying environmental conditions.

Device Isolation Techniques • The MOS transistors need to be electrically isolated during fabrication. • Isolation is necessary to prevent unwanted conduction paths between devices and to avoid creation of inversion layer outside channel sepration region and to reduce leackage currents • Active area is created, which is surronded by a relatively thick oxide barrier called the field oxide. • Ethced field oxide isolation. ( Grow Silicon Oxide and Etched away u Necessary). Disadvantage: Thickness of the field oxide leads to large Oxide steps at the boundry of Active and isolated regions. This leads to the cracking of layer (Hence Chip Failure) when metal/ Poly is deposited in next steps

Local Oxidation of Silicon (LOCOS) • Based on the Principal of selectively Growing the oxide rahter than etching. • Selectice Growth is achieved by shielding the Active area with Silicon Nitride (Si 3 N 4) • First Thin oxide is grown followed by deposition and patterning of Silicon Nitride (Si 3 N 4)

Local Oxidation of Silicon (LOCOS) Exposed area form the isolation region and doped with P Kind of impurities P

Local Oxidation of Silicon (LOCOS) Thick oxide is grown in next step where the area is not covered by Si 3 N 4. Birds Beak Region.

Local Oxidation of Silicon (LOCOS) Etching of Si 3 N 4 and thin Oxide. Most Popular Techniques. Later Some techniques are developed to control Bird’s Beak Region.

Summary • • • MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip!

References 1. 2. 3. 4. 5. 6. 7. 8. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT, Austin Community College, January 2, 1997. Semiconductor Processing with MKS Instruments, Inc. Worthington, Eric. “New CMP architecture addresses key process issues, ” Solid State Technology, January 1996. Leskonic, Sharon. “Overview of CMP Processing, ” SEMATECH Presentation, 1996. Gwozdz, Peter. “Semiconductor Processing Technology” SEMI, 1997. CVD Tungsten, Novellus Sales Brochure, 7/96. Fullman Company website. “Fullman Company - The Semiconductor Manufacturing Process, ” http: //www. fullman. com/semiconductors/index. html, 1997. Barrett, Craig R. “From Sand to Silicon: Manufacturing an Integrated Circuit, ” Scientific American Special Issue: The Solid State Century, January 22, 1998.

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