Extra Cache Coherence Examples In the following examples

Extra Cache Coherence Examples In the following examples there a couple questions. You can answer these for practice by emailing Colin at cdbryan@gmail. com.

MSI Protocol There are three processors. Each is reading/writing the same value from memory where r 1 means a read by processor 1 and w 3 means a write by processor 3. For simplicity sake, the memory location will be referred to as “value. ” The memory access stream is: r 1, r 2, w 3, r 2, w 1, w 2, r 3, r 2, r 1

r 1 P 2 P 3 Snooper Pr. Rd value Bus. Rd S Snooper Main Memory P 1 wants to read the value. The cache does not have itand generates a Bus. Rd for the data. Main memory controller provides the data. The data goes into the cache in the shared state.

r 2 P 1 P 3 P 2 Pr. Rd value S Snooper Bus. Rd value S Snooper Main Memory P 2 wants to read the value. Its cache does not have the data, so it places a Bus. Rd to notify other processors and ask for the data. The memory controller provides the data.

w 3 P 1 value Snooper P 3 P 2 S I value S Snooper I value Pr. Wr M Snooper Bus. Rd. X Main Memory P 3 wants to write the value. It places a Bus. Rd. X to get exclusive access and the most recent copy of the data. The caches of P 1 and P 2 see the Bus. Rd. X and invalidate their copies. Because the value is still up-todate in memory, memory provides the data.

r 2 P 1 value Snooper P 2 I value Bus. Rd Snooper Pr. Rd S I Flush P 3 value M S Snooper Main Memory P 2 wants to read the value. P 3’s cache has the most up -to-date copy and will provide it. P 2’s cache puts a Bus. Rd on the bus. P 3’s cache snoops this and cancels the memory access because it will provide the data. P 3’s cache flushes the data to the bus.

w 1 P 1 value Bus. Rd. X Snooper Pr. Wr I M P 3 P 2 value S Snooper I value S I Snooper Main Memory P 1 wants to write to its cache. The cache places a Bus. Rd. X on the bus to gain exclusive access and the most up-to-date value. Main memory is not stale so it provides the data. The snoopers for P 2 and P 3 see the Bus. Rd. X and invalidate their copies in cache.

w 2 P 1 value Snooper P 2 M I Flush value Snooper Pr. Wr I M Bus. Rd. X P 3 value I Snooper Main Memory P 2 wants to write the value. Its cache places a Bus. Rd. X to get exclusive access and the most recent copy of the data. P 1’s snooper sees the Bus. Rd. X and flushes the data to the bus. Also, it invalides the data in its cache and cancels the memory access.

r 3 P 1 value Snooper P 3 P 2 I value Snooper M S Flush value Snooper Pr. Rd I S Bus. Rd Main Memory P 3 wants to read the value. Its cache does not have a valid copy, so it places a Bus. Rd on the bus. P 2 has a modified copy, so it flushes the data on the bus and changes the status of the cache data to shared. The flush cancels the memory accecss and updates the data in memory as well.

r 2 P 1 value Snooper P 2 I value Pr. Rd S Snooper P 3 value S Snooper Main Memory P 2 wants to read the value. Its cache has an up-to-date copy. No bus transactions need to take place as there is no cache miss.

r 1 P 1 value Bus. Rd Snooper Pr. Rd I S P 3 P 2 value S Snooper Main Memory P 1 wants to read the value. The cache does not have it, so it places a Bus. Rd onto the bus for the data. The memory controller provides the data as it has an up-todate copy. The data goes into the cache in the shared state.

MESI Protocol There are three processors. Each is loading or storing different words from memory given as w 0, w 1, and w 2. These all map to the same location in cache.

The memory accesses are as follows: P 1: ld w 0, P 3: ld w 2 P 1: st w 0, P 2: st w 2 P 2 st w 2, P 3 ld w 0 P 3: st w 0 P 1: ld w 2 P 2: ld w 1 P 3: ld w 1

P 1 ld w 0 P 3 ld w 2 P 1 P 2 P 3 Pr. Rd w 0 Bus. Rd(¬S) E Snooper w 2 Snooper E Snooper Bus. Rd (¬S) Main Memory In both loads, a cache miss happens so each cache puts a Bus. Rd onto the bus for the information. Main memory is the owner and will provide the up-to-date data. P 1’s cache loads w 0 in the E state. P 3’s cache loads w 2 in the E state as well.

P 1 st w 0 P 2 st w 2 P 1 P 2 P 3 Pr. Wr w 0 Snooper E M Bus. Rd. X w 2 M Snooper w 2 Snooper E I Flush Main Memory P 1 has w 0 in the exclusive state, so on the cache hit, it does not need to have a bus transaction. w 2 is not in P 2’s cache, so the cache places a Bus. Rd. X to gain exclusive access. Main memory provides the data because it is not stale even though P 3’s cache has the data. w 2 is loaded in M state and P 3’s cache invalidates its copy of w 2.

P 2 st w 0 P 3 ld w 0 P 1 P 2 P 3 Pr. Rd Pr. Wr w 0 M S Snooper w 2 M Snooper Flush w 2 w 0 I Snooper S Bus. Rd(S) Main Memory P 2 executes another store to w 2. It already has exclusive access to w 2 and the store results in a cache hit. No bus transaction is issued by P 2’s cache. P 3 wants to load w 0. This results in a cache miss and the cache issues a Bus. Rd transaction. P 1’s cache asserts the S signal because it has a dirty w 0 and provides the up-to-date data through a flush. P 1 changes its state to S. P 3’s cache loads w 0 in the S state.

P 3 st w 0 P 1 P 2 P 3 Pr. Wr w 0 Snooper S I w 2 M Snooper w 0 S M Snooper Main Memory P 3 executes a store to w 0. Both P 1 and P 3 have an up-to-date, unmodified w 0. What bus transactions are needed?

P 1 ld w 2 P 1 P 2 P 3 Pr. Rd w 0 w 2 S Bus. Rd(S) Snooper S Flush w 2 M S Snooper w 0 M Snooper Main Memory P 1 wants to load w 2. P 1’s cache does not have w 2, so it issues a Bus. Rd transaction. P 2’s cache turns on the S signal, so P 1’s cache knows to load w 2 in the S state. P 2’s cache provides w 2 for P 1 and cancels the access to main memory through a Flush.

P 2 ld w 1 P 2 P 3 Pr. Rd w 2 Snooper w 2 w 1 S E S Bus. Rd(¬S) Snooper w 0 M Snooper Main Memory P 2 wants to load w 1. This generates a cache miss. P 2’s cache issues a Bus. Rd transaction. The S signal is not asserted, so it knows that it has exclusive access to w 1. Main memory provides the data for w 1. Should the state of w 2 be changed in P 1 because it is the only cache that has a copy of w 2?

P 3 ld w 1 P 2 P 3 Pr. Rd w 2 Snooper S w 1 Flush E S Snooper Bus. Rd(S) w 0 w 1 M S Snooper Main Memory P 3 wants to load w 1. This generates a cache miss. P 3’s cache issues a Bus. Rd transaction. The S signal is asserted by P 2’s cache, so P 3’s cache knows that it will load w 1 in the S state. Main memory provides the data for w 1 because its copy is not stale. P 3 flushes w 0 before loading w 1. Flush

Dragon Protocol In this system there are 3 processors. Each is loading or storing from memory locations w 0, w 1, w 2, and w 3. w 0 and w 1 are on the same cache line and are loaded at the same time. Likewise for w 2 and w 3. The two cache lines map to the same location in cache.

P 1 ld w 2 P 1 P 2 P 3 Pr. Rd w 2, w 3 Bus. Rd(¬S) Snooper E Snooper Main Memory P 1 wants to load w 2. This generates a cache miss and P 1’s cache issues a Bus. Rd bus transaction. The S signal is not asserted, so the cache knows to load w 2 and w 3 in the E state.

P 2 ld w 0 P 1 P 2 P 3 Pr. Rd w 2, w 3 Snooper E w 0, w 1 E Bus. Rd(¬S) Snooper Main Memory P 2 wants to load w 0. This generates a cache miss and P 1’s cache issues a Bus. Rd bus transaction. The S signal is not asserted, so the cache knows to load w 0 and w 1 in the E state.

P 3 st w 1 P 2 P 3 Pr. Wr w 2, w 3 Snooper w 0, w 1 E Update E Sc Snooper w 0, w 1 Sm Bus. Upd Snooper Bus. Rd(S) Main Memory P 3 wants to store w 1. This generates a cache miss. Memory will provide the data as no other cache has this line in a modified state. After storing the new value of w 1, P 3’s cache issues a Bus. Upd. P 2 snoops this and updates its cache with the updated w 1.

P 1 st w 3 P 1 P 2 P 3 Pr. Rd w 2, w 3 Snooper E M w 0, w 1 Sc Snooper w 0, w 1 Sm Snooper Main Memory P 1 issues store w 3. It has exclusive access to this cache line. What bus transactions does P 1’s cache issue?

P 2 ld w 3 P 1 P 2 P 3 Pr. Rd w 2, w 3 Snooper M Sm Flush w 2, w 0, w 3 w 1 Sc Snooper Bus. Rd(S) w 0, w 1 Sm ? ? ? Snooper Main Memory P 2 wants to load w 3. This generates a cache miss. P 2’s cache issues a Bus. Rd transaction. P 1 asserts the S signal, so P 2 will load the cache line in Sc state. P 1’s cache has a modified version of the cache line, so it will provide the data for P 2 with a flush transaction. P 1’s cache will update the line’s state to Sm. Should P 3 change w 0/w 1’s state to M?

P 2 ld w 2 P 3 st w 0 P 1 P 2 P 3 Pr. Rd w 2, w 3 Sm Snooper Pr. Wr w 2, w 3 Sc Snooper w 0, w 1 ? Snooper Main Memory P 2 wants to load w 2. P 3 wants to store w 0. What are the necessary bus transactions and cache updates that need to take place?