Experiment 7 Design of Binary Arithmetic Circuits Experiment
Experiment 7 Design of Binary Arithmetic Circuits
Experiment 6 Overview: • The Point: you used some relatively simple VHDL models to implement some relatively complicated circuits. • Include block diagrams • Concurrency = Concurrency (CSA) • VHDL code should look perfect – – – Properly indentation Commented Title banner (names, description, etc) No line wrap! Self commented names
Instructional Objectives: • To use concurrent VHDL statements in the design of arithmetic circuits • To design a Half Adder, Full Adder, 4 -bit Ripple Carry Adder, and 4 -bit Comparator
Digital Alarm System 7 -Seg Decoder Priority Encoder Connect to ground 4 switches (sensors) I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 B 3 B 2 B 1 B 0 Y 2 Y 1 Y 0 AA-AG CATH STROBE Alarm Control Key Comparator Break-in 4 switches (access code) I 3 I 2 I 1 I 0 EQ Experiment 7 P 3 OFF/ON_L Armed Alarm
Binary Addition Given two 4 -bit numbers, their sum A+B is calculated as follows c 2 c 1 c 0 cout a 3 a 2 a 1 a 0 + b 3 b 2 b 1 b 0 s 3 s 2 s 1 s 0
Half Adder A device, called a Half Adder, can be design to add a 0+b 0 in the least significant stage of the addition problem. Inputs: Output: ai, bi ci, si Obtain equations for ci and si from the truth table for the half adder.
Full Adder A device, called a Full Adder, can be design to add ai+bi, for i>0 stages of the addition problem. Inputs: Output: ai, bi, ci-1(carry in to that stage) ci, si Obtain equations for ci and si from the truth table for the full adder.
4 -Bit Ripple Carry Adder Use one Half Adder (for the least significant stage) and three Full Adders. Propagate the carry through the circuit: ripple How many gate propagation delays before the carry out is valid?
4 -Bit Comparator Given two 4 -bit binary numbers, A and B, determine if they are equal. Multiple solutions: – Subtract B from A and test for zero result – Use XOR gates to do a bitwise comparison
VHDL Concurrent Statement Refresher ARCHITECTURE mad_hatter OF myhalfadder IS BEGIN concurrent statement 1; -- half adder sum equation concurrent statement 2; -- half adder carry equation END myarch;
VHDL Structural Modeling • Reflects modern digital circuit design • Supports readability, understandability, reuse of code • Supports preferred digital design approach: hierarchical design • Allows for the use of library-based modules • Allows for easy scalability of design • Utilizes software design techniques • Xilinx schematic capture software not reliable
VHDL Structural Modeling Similar to higher level language programming Example circuit
VHDL Code for “Modules”
Final VHDL Code
XCRPlus Development Board Carry out 4 -bit sum Of A+B A B
Experiment 7 Overview P 1: Design, test, and implement a Half Adder P 2: Design, test, and implement a Full Adder P 3: Design and implement a 4 -bit Ripple Carry Adder Using Structural Modeling (Modelsim printout) P 4: Design and implement a 4 -bit Comparator Save for use in Experiment 9
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